SRAM Butterfly Architecture for Speed and Density Trade-offs
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Solution Overview
Problem
Traditional SRAM designs either prioritize high density at the expense of speed or high speed at the cost of area, failing to efficiently integrate both high speed and high density bitcells within a single memory architecture.
Innovation Solution
The implementation of a butterfly architecture in SRAM that combines high speed and high density bitcell arrays, sharing common functional units like row decoders, clock generators, and latches, with self-timed paths tuned for each array to manage Process-Voltage-Temperature variations and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a bitcell is optimized for high density, then the memory density is improved, but the read and write operation speed deteriorates
Solution Approach 1:
The SRAM is divided into two separate bitcell arrays: a first bitcell array optimized for high density and a second bitcell array optimized for high speed. Each array is independently segmented with its own self-timed path, allowing them to operate at different performance levels simultaneously without interfering with each other.
Solution Approach 2:
Different regions of the SRAM (different bitcell arrays) are given different local qualities - one region is optimized for density with smaller bitcells, while another region is optimized for speed with larger bitcells. This allows each part of the system to have the properties needed for its specific function.
2Speed
If a bitcell is optimized for high speed operation, then the operation speed is improved, but the die area occupied increases
Solution Approach 1:
The SRAM is divided into two separate bitcell arrays: a first bitcell array optimized for high density and a second bitcell array optimized for high speed. Each array is independently segmented with its own self-timed path, allowing them to operate at different performance levels simultaneously without interfering with each other.
Solution Approach 2:
Different regions of the SRAM (different bitcell arrays) are given different local qualities - one region is optimized for density with smaller bitcells, while another region is optimized for speed with larger bitcells. This allows each part of the system to have the properties needed for its specific function.
3Device complexity
If a single SRAM architecture uses uniform bitcells, then the design simplicity is maintained, but the ability to balance speed and density is reduced
Solution Approach 1:
The SRAM is divided into two separate bitcell arrays: a first bitcell array optimized for high density and a second bitcell array optimized for high speed. Each array is independently segmented with its own self-timed path, allowing them to operate at different performance levels simultaneously without interfering with each other.
Solution Approach 2:
The shared functional units (row decoders, clock generators, input buffers, latches, and row access circuits) serve multiple functions by supporting both the high-density array and the high-speed array, reducing overall device complexity while maintaining the benefits of heterogeneous bitcell designs.
Data Source
AI summary
An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed. The SRAM further includes a first set of wordline drivers coupled to the first bitcell array, a second set of wordline drivers coupled to the second bitcell array, and a row decoder coupled to both the first and second bitcell arrays.