Low Voltage SRAM Cache Compression and ECC Segmentation

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Solution Overview

Problem

Low voltage operation of SRAM-based caches leads to persistent bit errors, increasing power consumption and reducing reliability, as the number of faults grows exponentially with decreasing voltage and operating frequency.

Innovation Solution

Implementing data compression and an error correction code cache to store error-recovery metadata, allowing the cache to operate at lower voltages while maintaining reliability by prioritizing the placement of compressed data in fault-free subportions of cache lines and dynamically managing error protection resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If supply voltage is lowered to reduce power consumption, then power consumption decreases, but bit error rate increases exponentially

Engineering Contradiction:
Improvepower consumptionVSAvoidbit error rate
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The cache is divided into multiple subportions (e.g., half-cache or quarter-cache) within each cache line. Error correction code (ECC) metadata is stored in dedicated ECC subportions, while data is stored in data subportions. This segmentation allows the system to operate at low voltage with ECC protection for only the critical metadata portions, rather than protecting entire cache lines, thus reducing power consumption while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different parts of the cache structure receive different levels of error protection. ECC metadata in ECC subportions is protected with full ECC coverage, while data in data subportions uses compressed or reduced ECC coverage. This local differentiation optimizes power consumption by applying error protection only where most critical, enabling low-voltage operation without sacrificing overall reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If error correction code cache is used to protect against low voltage faults, then reliability improves, but device complexity increases

Engineering Contradiction:
Improvefault toleranceVSAvoidcache structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Each cache line is segmented into ECC subportions and data subportions. ECC subportions store compressed ECC metadata and are fully protected, while data subportions store application data with reduced protection. This segmentation reduces the total amount of ECC metadata needed compared to protecting entire cache lines, thereby reducing complexity while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The ECC coverage parameter is dynamically adjusted based on the subportion type. ECC subportions use full ECC coverage for maximum reliability, while data subportions use compressed or reduced ECC coverage. This parameter change allows the system to achieve acceptable reliability with less ECC overhead, reducing device complexity.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If compressed data is placed in faulted subportions of cache lines, then cache utilization improves, but performance loss increases due to decompression overhead

Engineering Contradiction:
Improvecache utilizationVSAvoiddecompression time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Cache lines are segmented into faulted subportions and non-faulted subportions. Compressed data is placed only in non-faulted subportions to avoid decompression of corrupted data. This selective placement improves cache utilization by keeping faulted lines enabled while minimizing decompression overhead by only decompressing data from reliable subportions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts and separates ECC metadata from data, storing them in different subportions. Compressed data is extracted and placed only in non-faulted subportions, leaving faulted subportions for ECC metadata or unused. This extraction improves cache utilization by enabling faulted lines while reducing unnecessary decompression operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10884940B2Method and apparatus for using compression to improve performance of low voltage caches
Publication Date: 2021.01.05 ADVANCED MICRO DEVICES INC
  • US10884940B2 patent drawing
  • US10884940B2 patent drawing
  • US10884940B2 patent drawing

AI summary

A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.