On-Die SRAM Cache for DRAM Row Buffer Limitations
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Solution Overview
Problem
The efficiency of memory access in DRAM devices is limited by the size of the single row buffer used for caching, which restricts the effectiveness of the caching scheme.
Innovation Solution
Implementing a dedicated on-die low latency memory, such as SRAM, as a cache for DRAM devices to cache data from main memory banks, enhancing the memory interface with cache hints and eviction commands to manage cache data effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single row buffer is used for caching in DRAM devices, then the device complexity is kept simple, but the memory access efficiency is limited
Solution Approach 1:
The patent divides the caching structure into multiple segmentable row buffers instead of using a single row buffer. This segmentation allows the cache to store multiple rows simultaneously, increasing the cache capacity and improving memory access efficiency without requiring a complete redesign of the caching mechanism.
Solution Approach 2:
The patent implements a hierarchical caching structure where multiple row buffers are organized in a nested manner within the DRAM device. This nested structure allows for efficient data retrieval by first checking the closer row buffers and then accessing the main memory banks, thereby improving access efficiency while maintaining a structured and manageable complexity.
2Productivity
If the row buffer size is increased to improve caching capacity, then memory access efficiency improves, but the area occupied by the buffer increases
Solution Approach 1:
Instead of increasing the size of a single row buffer, the patent segments the caching capacity across multiple smaller row buffers. This approach achieves the same total caching capacity while distributing the area requirement across multiple compact units, reducing the peak area occupation and improving spatial utilization.
Solution Approach 2:
The patent transitions from a single-dimension buffering approach (one large buffer) to a multi-dimensional approach (multiple smaller buffers arranged in a hierarchy). This dimensional change allows the system to achieve high caching capacity without proportionally increasing the area occupied by any single buffer component.
Data Source
AI summary
An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.