CMOS SRAM Cell Body Biasing for Current Ratio
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Solution Overview
Problem
CMOS SRAM cells face challenges in achieving a sufficient NMOS to PMOS saturated current ratio (Idsat ratio) at low operating voltages and small node technologies, leading to increased SRAM cell size and area, which is undesirable.
Innovation Solution
The implementation of a memory cell design that includes a PMOS transistor in N-type semiconductor material and an NMOS transistor in P-type semiconductor material, with a well bias voltage applied to reverse body-bias the PMOS transistor or forward body-bias the NMOS transistor, increasing the saturation current ratio between NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the NMOS pull-down transistors are made wider to increase saturation current, then the NMOS to PMOS saturation current ratio is improved, but the SRAM cell size increases
Solution Approach 1:
The patent applies reverse body-bias to the PMOS pull-up transistors by connecting their P-type wells to a bias voltage that is higher than their source voltage. This parameter change in the well voltage modifies the threshold voltage and reduces the saturation current of PMOS transistors, thereby increasing the NMOS to PMOS current ratio without requiring larger transistor dimensions or increasing cell area
2Reliability
If the gate length of PMOS pull-up transistors is made longer to reduce saturation current, then the NMOS to PMOS saturation current ratio is improved, but the SRAM cell area increases
Solution Approach 1:
Instead of changing the geometric dimensions (gate length) of the PMOS transistors, the patent changes the electrical parameter (well bias voltage) to control the saturation current. The reverse body-bias applied to the P-type wells dynamically adjusts the PMOS current characteristics without affecting the physical layout or cell area
3Reliability
If the threshold voltage of PMOS pull-up transistors is increased to reduce saturation current, then the NMOS to PMOS saturation current ratio is improved, but additional masking and processing steps are required
Solution Approach 1:
The patent incorporates well bias terminals and connection structures into the standard CMOS fabrication process during the formation of P-type wells. This preliminary inclusion of biasing infrastructure allows dynamic threshold voltage control to be achieved without adding subsequent masking or processing steps, as the biasing capability is built-in from the beginning
Solution Approach 2:
The patent implements dynamic control of PMOS threshold voltage through externally applied reverse body-bias. Instead of using fixed threshold voltages determined by static fabrication parameters, the threshold voltage can be dynamically adjusted during operation, providing flexibility in current ratio optimization without additional processing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the NMOS to PMOS saturation current ratio, reducing PMOS saturation current by 25% and increasing the effective ratio, allowing for smaller SRAM cell size with improved READ/WRITE performance and reduced cell area, while maintaining efficient operation at low voltages.
Implementation Method 1
a well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material is configured so as to provide a well bias voltage not equal to the PMOS bias voltage or to the NMOS bias voltage to reverse body-bias the PMOS transistor or to forward body-bias the NMOS transistor
Data Source
AI summary
A memory cell in an integrated circuit has a first PMOS transistor formed in N-type semiconductor material and a first NMOS transistor formed in P-type semiconductor material. A well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material provides a well bias voltage not equal to the PMOS bias voltage or to the NMOS bias voltage to reverse body-bias the PMOS transistor or to forward body-bias the NMOS transistor.