SRAM Cell Variation Characterization Using Digital Comparator
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Solution Overview
Problem
Current methods for characterizing local and systematic variations in SRAM cells are inefficient, requiring complex analog measurements and being unsuitable for in-line or on-chip characterization, which hinders the development of robust SRAM technology due to increased test-time and inability to accurately predict variations in cell layout.
Innovation Solution
A digital measurement technique using a comparator circuit and decoding logic to estimate standard deviation and mean offset voltage of transistors, allowing for simultaneous characterization of local random and systematic variations in SRAM cells with minimal changes to the cell layout, enabling fast and reliable on-chip, in-line testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional current difference measurement methods are used to characterize local random variation, then measurement precision can be achieved, but test time increases significantly and the method becomes unsuitable for in-line or on-chip characterization
Solution Approach 1:
The patent replaces complex analog current measurement systems with a digital voltage comparison system. Instead of measuring current differences using sophisticated analog instruments and extracting threshold voltage through complex data analysis, the invention uses a digital comparator to directly compare voltages generated by the transistors under test. This substitution of measurement domain (from analog current to digital voltage) dramatically reduces test time while maintaining characterization accuracy
Solution Approach 2:
The patent changes the measurement parameter from current to voltage. By configuring the transistors in a specific circuit arrangement where their output voltages can be directly compared, the method transforms the measurement quantity. This parameter change enables the use of simple digital comparators instead of complex analog measurement systems, reducing test time significantly while preserving the ability to characterize local random variation
2Ease of manufacture
If ring-oscillator frequency measurement is used to characterize systematic variation, then measurement can be performed, but the method cannot accurately predict systematic variation in SRAM cells due to layout differences
Solution Approach 1:
The patent applies local quality by creating characterization circuits that match the specific SRAM cell layout being tested. Instead of using generic ring-oscillators distributed across the chip, the invention places transistor pairs directly within or adjacent to the SRAM cells, ensuring the characterization circuit experiences the same local systematic variations (such as stress, temperature gradients, and lithographic effects) as the actual memory cells. This local matching dramatically improves prediction accuracy
3Measurement precision
If complex data extraction tools are used to extract threshold voltage from current difference, then measurement precision can be achieved, but device complexity and measurement system complexity increase significantly
Solution Approach 1:
The patent replaces the complex measurement system (current measurement instruments and data extraction software) with a simple digital comparator circuit. The complex analog-to-digital conversion and iterative data analysis processes are substituted with a direct digital voltage comparison, eliminating the need for sophisticated measurement equipment and complex computational tools while maintaining threshold voltage characterization accuracy
Data Source
AI summary
A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.