SRAM Cell FinFET Mobility Control via Counter-Doping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
FinFET structures face challenges in implementing strong p-type transistors in certain circuit types, such as SRAM cells, due to discretization of effective transistor width and the need for specific current/performance ratios, which results in increased area and power dissipation, and the mobility improvement from undoped fins is compromised by doping.
Innovation Solution
The use of counter-doping implantations with a dopant species of opposite polarity and the introduction of interstitials or electrically non-active materials like germanium or carbon in the channel region to reduce charge carrier mobility, allowing for selective reduction of drive current and minimizing side effects on threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If p-type FinFETs are used to achieve strong transistor performance, then current drive capability is improved, but area and power dissipation increase due to discretization of effective transistor width
Solution Approach 1:
The patent applies selective doping to specific fin regions to create local variations in charge carrier mobility. By doping only portions of the fin structure rather than uniformly, the invention achieves localized current control while maintaining overall area efficiency. This resolves the contradiction by enabling strong current drive in specific regions without proportionally increasing total transistor area.
Solution Approach 2:
The patent modifies the charge carrier mobility parameter through selective doping of fin regions. By changing the doping concentration and distribution in specific areas, the invention optimizes current drive capability while controlling area usage. This parameter change allows achieving desired current levels without the area penalty that would result from uniformly strong transistor design.
2Reliability
If fins are doped to adjust threshold voltage, then threshold voltage control is improved, but charge carrier mobility decreases due to increased scattering
Solution Approach 1:
The patent implements selective doping where only specific regions of the fin structure are doped rather than the entire fin. This local quality approach allows threshold voltage adjustment in critical regions while leaving other regions undoped to maintain high charge carrier mobility. The spatial differentiation resolves the contradiction between threshold voltage control and mobility preservation.
Solution Approach 2:
The fin structure is segmented into doped and undoped regions, each serving different functional purposes. The doped segments provide threshold voltage control, while the undoped segments preserve high mobility. This segmentation strategy allows simultaneous achievement of both threshold voltage adjustment and mobility maintenance that would be impossible with uniform doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the achievement of required performance ratios in SRAM cells by reducing charge carrier mobility in specific transistors, allowing for smaller gate electrodes and reduced power dissipation while maintaining the benefits of undoped fin mobility, thus optimizing transistor performance and area efficiency.
Implementation Method 1
counter-doping implantations with a dopant species of opposite polarity to reduce charge carrier mobility
Implementation Method 2
The mobility can be reduced by using a higher dose, also called an excess dose, than required for a threshold voltage adjustment, followed by a counter-doping implantation
Implementation Method 3
The mobility can also be reduced by introducing interstitials and damage to result in, for example, electrically non-active scatter centers
Data Source
AI summary
One or more embodiments relate to a static random access memory cell comprising: a first inverter including a first n-channel pull-down transistor coupled between a first node and a ground voltage; a second inverter including a second n-channel pull-down transistor coupled between a second node and the ground voltage; a first n-channel access transistor coupled between a first bit line and the first node of the first inverter, a fin of the first n-channel access transistor having a lower charge carrier mobility than a fin of the first n-channel pull-down transistor; and a second n-channel access transistor coupled between a second bit line and the second node of the second inverter, a fin of the second n-channel access transistor having a lower charge carrier mobility than a fin of the second n-channel pull-down transistor.