SRAM Cell Coupling Capacitance for Write Boost
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Solution Overview
Problem
Existing SRAM cells face challenges in maintaining stability during read operations while enabling efficient writing, as making cells more stable during reads complicates write operations, and there is a need to reduce area and power consumption while boosting word line voltage for robust write capabilities.
Innovation Solution
The integration of a coupling capacitance between write and read/write word lines, along with an overdrive module to provide an overdrive voltage on the read/write word line during write cycles, facilitates a boosted double-sided write capability by charging the capacitance initially and redistributing charge for voltage boosting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SRAM cell is made more stable during read operations, then read stability is improved, but write operation difficulty increases
Solution Approach 1:
The patent applies dynamics by making the word line voltage adjustable based on operation mode. During read operations, the word line is held at a lower voltage to ensure stability. During write operations, the word line voltage is dynamically boosted to a higher level to enable robust writing. This dynamic voltage adjustment resolves the contradiction between read stability and write ease by adapting the cell characteristics to the current operation requirements.
Solution Approach 2:
The patent changes the voltage parameter of the word line based on the operation mode. A voltage boost mechanism is introduced that increases the word line voltage from a standard read level to an elevated write level. This parameter change enables the cell to maintain stability during reads while providing the necessary drive strength for writes, thus resolving the contradiction between reliability during reads and ease of write operations.
2Reliability
If word line voltage is boosted for robust write capabilities, then write robustness is improved, but power consumption increases
Solution Approach 1:
The voltage boost is applied periodically and transiently only during write operations rather than continuously. The boost mechanism is activated only when a write operation is detected, provides the necessary voltage enhancement for robust writing, and then returns to the normal voltage level. This periodic application of the voltage boost achieves write robustness while minimizing overall power consumption compared to continuous high-voltage operation.
Solution Approach 2:
The voltage boost is prepared in advance through a charging circuit that pre-charges capacitors or stores energy in a battery-like structure before the write operation begins. This preliminary action ensures that when a write operation is needed, the boosted voltage is already available or can be quickly supplied, reducing the power consumption during the actual write operation compared to continuously maintaining high voltage.
3Reliability
If coupling capacitance is charged during initial part of write cycle, then overdrive voltage is provided for robust writing, but write cycle time increases
Solution Approach 1:
The coupling capacitance is charged during an initial part of the write cycle before the main write operation begins. This preliminary charging action prepares the overdrive voltage source in advance, so that when the main write operation starts, the voltage boost is already available or can be quickly supplied. This approach ensures robust writing while minimizing the time penalty, as the capacitance charging overlaps with or precedes the main write operation rather than adding to it.
Solution Approach 2:
The capacitance charging process is designed to occur continuously or in parallel with other operations, ensuring that the overdrive voltage is always ready when needed. By making the charging action continuous or overlapping with read operations or other non-critical periods, the system maintains useful action without significant time loss, achieving both robust writing and minimal write cycle time extension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability of SRAM cells during read operations while allowing robust write operations with minimal impact on speed and power consumption, achieving efficient area usage and improved write current.
Implementation Method 1
a coupling capacitance connected between the write word line and a detachable allocation of the read/write word line
Implementation Method 2
an overdrive module connected to charge the coupling capacitance and provide an overdrive voltage on the detachable allocation of the read/write word line during activation of the write word line
Data Source
AI summary
An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a read/write word line connected to provide row access to the array of SRAM cells. The SRAM also includes a coupling capacitance connected between the write word line and a detachable allocation of the read/write word line as well as an overdrive module connected to charge the coupling capacitance and provide an overdrive voltage on the detachable allocation of the read/write word line during activation of the write word line. A method of operating an integrated circuit having an SRAM includes providing an overdrive voltage on the detachable allocation of the read/write word line corresponding to a charge redistribution across the coupling capacitance during part of a write cycle.