SRAM Cell Structure Deep N-Well Soft Error Resilience
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing soft errors caused by excess charge carriers, such as alpha-particles and cosmic ray neutrons, which can corrupt data in SRAM devices, and existing solutions often require additional circuitry, processing, or increased power, compromising the design and efficiency of integrated circuits.
Innovation Solution
A memory cell structure is designed with a deep NWELL region and an SRAM cell that includes a specific arrangement of n-type and p-type metal oxide semiconductor transistors, inter-metal-dielectric layers, and a polyimide layer, optimizing the cell area and transistor ratios to enhance resilience to soft errors while maintaining power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuitry is added to reduce soft errors, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent changes physical parameters of the semiconductor structure, specifically creating a deep n-well region with controlled dimensions and positioning it beneath the SRAM cell. This structural parameter change provides inherent soft error protection through charge collection and shielding effects without adding complex circuitry.
Solution Approach 2:
The deep n-well region acts as an intermediary structure between the substrate and the SRAM cell, serving as a charge collection region that protects the memory cell from soft errors. This mediator absorbs excess charge carriers before they can corrupt the stored data, providing protection without requiring additional active circuitry.
2Reliability
If cell size is increased to increase capacitance, then reliability is improved, but area increases
Solution Approach 1:
Instead of increasing cell area in the planar dimension, the patent extends the protection mechanism into the vertical dimension by creating a deep n-well region that penetrates deep into the substrate. This dimensional transition allows charge collection without increasing the footprint of the memory cell.
Solution Approach 2:
The deep n-well region is nested beneath the SRAM cell structure, with the n-well containing p-well regions that in turn contain the transistors. This nested configuration allows the protection mechanism to be integrated within the existing cell structure without increasing external dimensions.
3Reliability
If additional capacitance structures are added, then reliability is improved, but device complexity increases
Solution Approach 1:
The deep n-well region serves multiple functions simultaneously: it acts as a charge collection region for soft error protection, provides substrate biasing, and serves as part of the transistor structure. This multi-functionality eliminates the need for separate capacitance structures while achieving soft error protection.
4Reliability
If resistance between source/drain and gate is increased, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent converts the potentially harmful effect of excess charge carriers into a beneficial mechanism by using the deep n-well to collect and contain these carriers. Instead of increasing resistance to prevent carrier injection, the n-well actively manages injected carriers through physical containment and recombination, avoiding power penalties.
Data Source
AI summary
An SRAM device includes an SRAM cell in a deep NWELL region in a substrate. PWELL regions in the SRAM cell occupy less than about 65% of the cell area of the SRAM cell. A ratio of a longer side of a cell area of the SRAM cell to a shorter side of the SRAM cell is larger than about 1.8. A total area of the active regions in the plurality of NMOS transistors in the SRAM cell occupies less than about 25% of the SRAM cell area. A ratio of the channel width of a pull up transistor in the SRAM cell to the channel width of a pull down transistor in the SRAM cell is greater than about 0.8. The SRAM cell further includes a boron free inter-layer-dielectric layer, an inter-metal-dielectric layer with dielectric constant less than about 3, and a polyimide layer with a thickness of less than about 20 microns.