SRAM Cell Leakage Reduction via Floating Reference Terminal
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Solution Overview
Problem
Conventional SRAM circuits face challenges in operating at low voltages due to issues such as half select disturb and leakage current, which hinder their efficiency in reducing power consumption for portable electronic devices.
Innovation Solution
The proposed SRAM cell design includes cross-coupled inverters, write and read transistors, and a wordline transistor configuration that enables specific voltage control during write and read operations, setting the reference terminal to floating during writes and precharging bitlines during reads to minimize disturb and leakage effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional SRAM circuit is operated at low voltage, then power consumption is reduced, but half select disturb and leakage current increase
Solution Approach 1:
The patent segments the write and read operations by introducing separate write transistors (first and second write transistors) and wordline transistors that can be independently controlled. This segmentation allows selective activation of transistors during write operations to prevent half-select disturb, while maintaining low voltage operation. The write transistors are selectively enabled based on write enable signals, isolating the storage nodes from bitlines when not actively writing.
Solution Approach 2:
The patent employs dynamic control of transistor enablement through write enable signals and wordline signals. The first and second write transistors are dynamically enabled during write operations and disabled during read operations or idle states. This dynamic control allows the circuit to adapt its conductivity and power consumption characteristics based on operational requirements, reducing leakage current when full write capability is not needed while maintaining reliability during active write operations.
2Duration of action of moving object
If conventional SRAM circuit is operated at low voltage, then battery life is extended, but leakage current increases
Solution Approach 1:
The patent implements preliminary action by precharging bitlines to a predetermined voltage level before read operations. The first and second bitlines are precharged to the same voltage level, and during read operations, the differential voltage developed on these precharged bitlines indicates the stored data. This preliminary precharging action ensures that the circuit is ready for rapid read operations while maintaining stable voltage levels that minimize leakage current during idle periods between operations.
Solution Approach 2:
The patent employs self-service mechanisms where the cross-coupled inverter structure automatically maintains stable voltage levels on storage nodes through positive feedback. The first inverter's output feeds back to the second inverter's input and vice versa, creating a bistable latch that maintains its state without continuous external control. This self-maintaining property reduces the need for active control signals, thereby reducing leakage current while preserving data integrity over extended periods.
Data Source
AI summary
A static random access memory cell includes first and second cross-coupled inverters, a write transistor and a read transistor. The first inverter has a first latch node and the second inverter has a second latch node. The write transistor is coupled in series with a wordline transistor between the first latch node of the first inverter and a bitline. The read transistor is coupled between the bitline and a reference terminal and has a control terminal coupled to the first latch node of the first inverter. A method of operating the static random access memory cell includes enabling the wordline transistor during a write operation, and enabling the write transistor during the write operation. The reference terminal is set to floating during the write operation.