SRAM Cell Latch Dynamics for Write Stability and Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional static random access memory (SRAM) cells face challenges in maintaining stability against read and half-selection disturbances while preserving write ability, often requiring additional circuitry that increases complexity and power consumption, and are hindered by the area overhead of voltage-boost write-assisted circuits.
Innovation Solution
A static random access memory cell design featuring a latch with specific transistor configurations and controlling signal lines, including a virtual ground line, bit lines, and word lines, allows for operational states that maintain stability and write ability without sacrificing performance, and reduces the need for a pumping capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional transistors are added to improve read stability, then read stability is improved, but write ability deteriorates
Solution Approach 1:
The patent employs dynamic control of transistor states during write operations. The access transistors are dynamically switched to create temporary write paths, and the latch transistors are dynamically controlled to temporarily open feedback loops during write operations, allowing data to be written without being locked by the stable feedback mechanism that protects against read disturbances.
Solution Approach 2:
The patent uses periodic control signals (word lines and bit lines) that are activated in specific sequences to enable different operational modes. During write operations, control signals are periodically applied to temporarily modify the circuit state, allowing data to be forced into the latch, followed by restoration of the stable feedback state to protect the stored data.
2Reliability
If conventional 10T static random access memory cell is used to avoid read and half-selection disturbances, then stability is improved, but write ability is sacrificed
Solution Approach 1:
The patent prepares the memory cell for write operations by pre-charging bit lines and pre-positioning control signals before the actual write operation. The access transistors are pre-enabled, and the latch is pre-prepared to accept data, ensuring that when the write signal arrives, the cell is in the optimal state to receive data without being constrained by stable feedback mechanisms.
3Ease of operation
If voltage-boost write-assisted circuit with pumping capacitor is used to improve write ability, then write ability is improved, but area overhead increases
Solution Approach 1:
The patent employs a write assist mechanism that utilizes the existing bit line charge and the natural capacitance of the latch nodes themselves, rather than requiring external pumping capacitors. The write operation leverages the inherent electrical properties of the memory cell components to achieve the necessary voltage boosting, making the cell self-sufficient for write operations without additional area-consuming components.
Data Source
AI summary
A static random access memory cell includes a controlling signal line unit, a latch and an access transistor unit. The first bottom transistor unit is controlled by the controlling signal line unit to change voltage levels of the first pseudo node and the second pseudo node. The second bottom transistor unit is controlled by the first internal node to perform connection and disconnection between the controlling signal line unit and the second pseudo node, and the second bottom transistor unit is controlled by the second internal node to perform connection and disconnection between the controlling signal line unit and the first pseudo node. The access transistor unit is controlled by the controlling signal line unit to perform connection and disconnection between the controlling signal line unit, the first pseudo node and the second pseudo node.