SRAM Cell Design for Low Operation Voltage
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Solution Overview
Problem
Conventional SRAM cells require high operation voltage, which becomes a bottleneck in designing new generation SRAMs with lower supply voltage, limiting the ability to reduce power consumption and advance semiconductor technology.
Innovation Solution
The SRAM cell design includes a first and second PMOS transistor with write and read switch modules, allowing for separate control of logic values at storage nodes, with NMOS transistors having lower threshold voltages to enable operation at a significantly lower voltage level for both read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional SRAM cell structure is used, then the SRAM can maintain stable memory states, but it requires high operation voltage which increases power consumption
Solution Approach 1:
The patent changes the voltage parameter by introducing a boosted write voltage (Vdd + Vboost) that is higher than the normal supply voltage. This boosted voltage is applied only during write operations to overcome the stability barrier and flip the latched state, while read and hold operations use the normal lower Vdd voltage. This parameter change enables the SRAM to operate with lower overall power consumption while maintaining stable memory states during normal operations.
2Use of energy by moving object
If supply voltage is reduced to lower power consumption, then power efficiency improves, but the operation voltage of conventional SRAM cells becomes a bottleneck
Solution Approach 1:
The patent introduces dynamic voltage control where the write voltage can be dynamically boosted above the normal supply voltage when needed. The circuit includes voltage boosting circuitry that activates only during write operations to provide the temporary high voltage needed for state flipping. This dynamic approach allows the SRAM to operate at low voltages during most operations while having the capability to temporarily exceed the normal voltage barrier when write operations are required.
Solution Approach 2:
The patent implements preliminary action by pre-charging the bit line to a high voltage level before write operations. This pre-charging prepares the circuit in advance so that when the write word line is activated, the pre-charged bit line can quickly deliver the necessary voltage to flip the latched state without requiring a sustained high voltage supply, thereby reducing overall power consumption.
3Reliability
If high operation voltage is used, then write operations can reliably flip memory states, but power consumption increases
Solution Approach 1:
The patent employs periodic action by applying the boosted write voltage only during the brief write operation window, rather than continuously. The voltage boosting is activated periodically only when a write operation is detected (when the write word line is asserted), and remains inactive during read operations and idle states. This periodic application of high voltage ensures reliable write operations while minimizing the time during which high power is consumed.
Data Source
AI summary
An SRAM cell includes: a first PMOS transistor having a source coupled to a supply voltage; a second PMOS transistor having a source coupled to the supply voltage, a drain coupled to a gate of the first PMOS transistor, and a gate coupled to a drain of the first PMOS transistor; a first write switch module coupled between the first PMOS transistor and a complementary supply voltage; a second write switch module coupled between the second PMOS transistor and the complementary supply voltage; and a read switch module coupled between the gate of the first PMOS transistor and a read bit line, wherein the first write switch module, the second write switch module, and the read switch module are controlled separately to write or read a logic value to or from one or more storage nodes at the drains of the first and second PMOS transistors.