SRAM Cell Layout Using Parallel Active Areas and Linear Intra-Cell Connections
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Solution Overview
Problem
Conventional SRAM cell layouts face challenges in miniaturization due to limitations in lithography and etching techniques, leading to issues like short circuits, current mismatch, leakage, and incompatibility with FinFETs, which restrict their use in smaller technology nodes and hinder the application of FinFETs in SRAM cells.
Innovation Solution
The proposed solution involves forming SRAM cells with transistors having parallel active areas and linear intra-cell connections that eliminate the need for butted contacts and active zags, allowing for parallel alignment of transistors and reduced complexity in processing, enabling the use of FinFETs and improving compatibility with smaller technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional SRAM cell layout is used, then the cell can be formed with standard transistors, but the cell size cannot be reduced further due to lithography and etching limitations
Solution Approach 1:
The patent transitions from a conventional planar SRAM layout to a three-dimensional FinFET structure. By stacking transistors vertically and using fins extending from the substrate, the design moves into the third dimension, allowing continued scaling of cell area without proportionally reducing lateral feature sizes that are constrained by lithography limits.
Solution Approach 2:
The patent divides the SRAM cell into multiple independent transistor components (pass-gate transistors, pull-down transistors, pull-up transistors) with distinct active areas. This segmentation allows each transistor to be optimized independently and connected through shared source/drain regions, reducing the need for additional interconnect structures and contacts that would consume valuable area.
2Ease of manufacture
If conventional SRAM layout with butted contacts is used, then transistors can be connected, but processing complexity increases with multiple etching steps
Solution Approach 1:
The patent merges the source and drain regions of adjacent transistors into shared structures. Specifically, the source/drain region of a pass-gate transistor serves dual purposes by also functioning as the source or drain of an adjacent pull-down transistor. This eliminates the need for separate butted contacts and reduces the number of etching steps required to create isolated contact holes.
Solution Approach 2:
The shared source/drain regions perform multiple functions simultaneously: they serve as electrical contacts for both the pass-gate transistor and the pull-down transistor, and they provide structural support for the gate electrodes. This multi-functionality reduces the overall component count and simplifies the fabrication process.
3Adaptability or versatility
If active zags are created in transistor active areas, then layout flexibility is improved, but current mismatch and leakage problems occur
Solution Approach 1:
The patent employs asymmetric active area designs where the pass-gate transistor and pull-down transistor share a common source/drain region with different geometries optimized for their respective functions. The active area shapes are deliberately made asymmetric to achieve both layout flexibility and proper current matching, avoiding the need for symmetric zags that cause leakage at sharp corners.
Solution Approach 2:
Different regions of the active areas are given different qualities and dimensions. The active area of the pass-gate transistor is designed with specific width and length characteristics optimized for fast switching, while the adjacent pull-down transistor active area is optimized for current drive strength. This local optimization allows each transistor to perform its function reliably without requiring uniform zag structures throughout.
4Area of moving object
If contact size is reduced to enable smaller cell dimensions, then cell area decreases, but overlay with gate electrode spacers causes performance degradation
Solution Approach 1:
By moving to a three-dimensional FinFET architecture with vertically extending fins, the patent reduces the lateral footprint of each transistor. This vertical stacking allows the cell area to be reduced without proportionally reducing the lateral dimensions of critical features like contacts and spacers, maintaining adequate overlay margins while achieving smaller overall cell size.
Data Source
AI summary
An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.