SRAM Cell Static Noise Margin via Dynamic PMOS Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM cells face a trade-off between improving static noise margin and write margin, with increased cell area and difficulty in discharging nodes during data write, due to the separation of PMOS transistors' wells and limited current driving ability.
Innovation Solution
Incorporating additional PMOS transistors connected to control signals that adjust the electric potential of nodes during write and read operations, allowing for increased static noise margin and write margin without significant area expansion, by using a CMOS inverter structure with PMOS and NMOS transistors and an additional transistor control circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the current driving ability of load transistors is increased to improve static noise margin, then the ability of nodes to keep to High is improved, but the discharging of nodes becomes difficult which reduces write margin
Solution Approach 1:
The patent introduces dynamic control of load transistor current driving ability through control signals (S1, S2) that adjust the on-resistance of additional PMOS transistors (P1, P2) based on operation mode (read/write/hold). During write operations, the control signals reduce the current driving ability to facilitate node discharging, while during read operations, the current driving ability is increased to improve static noise margin and data hold stability.
Solution Approach 2:
The patent changes the electrical parameters (on-resistance, current driving ability) of the load transistor circuit by introducing additional controllable PMOS transistors in series with the original load transistors. The control signals dynamically adjust these parameters to match the required operation mode, enabling simultaneous optimization of static noise margin and write margin.
2Reliability
If additional PMOS transistors are added to improve static noise margin and write margin, then both margins are enhanced, but the cell area increases
Solution Approach 1:
The patent merges the additional controllable PMOS transistors (P1, P2) with the existing load transistor circuit structure. The additional transistors are integrated into the same well region and share common control mechanisms with the original load transistors, allowing area-efficient implementation while achieving improved performance.
Solution Approach 2:
The additional PMOS transistors serve multiple functions: they act as load transistors during hold operations, as current limiting elements during write operations, and as static noise margin enhancement elements during read operations. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby minimizing area increase.
3Reliability
If PMOS transistors' wells are separated to improve device performance, then the current driving ability is enhanced, but the manufacturing complexity and area increase
Solution Approach 1:
The patent combines multiple PMOS transistors (original load transistors and additional controllable transistors) into a single shared well structure, eliminating the need for well separation. The control signals selectively activate specific transistors within the shared well to achieve the desired current driving ability without requiring physically separated wells.
Data Source
AI summary
Additional transistors P1 and P2 which are PMOS transistors are connected to load transistors PL1 and PL2 which are PMOS transistors such that drain electrodes of the additional transistors P1 and P2 and drain electrodes of the load transistors PL1 and PL2 are connected at a node 1 and a node 2 while gate electrodes of the additional transistors P1 and P2 and gate electrodes of the load transistors PL1 and PL2 are connected at the node 1 and the node 2. A source electrode of the additional transistor P1 is connected to an additional transistor control circuit, which is provided for each column. The additional transistor control circuit sets control signals S1 and S2 to the H level in other times than data write so that the additional transistor P1 or P2 compensates the load transistor PL1 or PL2, thereby increasing the static margin. In data write, the additional transistor control circuit sets the control signals S1 and S2 to the low level, thereby preventing the additional transistors from hindering the data write, and thus increasing the write margin.