SRAM Cell Routing Layout to Reduce RC Delay and Coupling Noise
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Solution Overview
Problem
As ICs become smaller and more complex, issues such as cross talk and wiring resistance in SRAM devices, particularly due to RC delay and coupling noise from Word lines and Bit lines, hinder performance and limit scaling ratio.
Innovation Solution
The integrated circuit design positions Word lines and high-voltage power lines on one side of the transistors and Bit lines and low-voltage power lines on the other side, with edge cells having tap structures to connect these lines efficiently, reducing resistance and improving routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If routing conductors (Word lines and Bit lines) are used in SRAM devices, then data storage function is achieved, but RC delay and coupling noise increase
Solution Approach 1:
The patent divides the routing conductors into two separate layers: first routing conductors (Word lines) and second routing conductors (Bit lines) are placed in different layers of the substrate. This segmentation spatially separates the conductors to reduce coupling noise and RC delay while maintaining the data storage function through proper interconnection.
Solution Approach 2:
The patent transitions from planar routing to three-dimensional routing by utilizing multiple layers of the substrate. First routing conductors are formed in a first layer and second routing conductors in a second layer, adding the vertical dimension to reduce electromagnetic coupling and RC delays between conductors.
2Area of moving object
If IC scaling is performed to make ICs smaller, then integration density increases, but wiring resistance and cross talk effects worsen
Solution Approach 1:
The patent employs multi-layer routing structures where conductors are distributed across different vertical layers. This three-dimensional arrangement allows for reduced inter-conductor spacing in the horizontal plane while maintaining adequate separation through the vertical dimension, thereby reducing wiring resistance and cross-talk effects during IC scaling.
Solution Approach 2:
The patent applies different routing configurations to different regions of the IC. First routing conductors and second routing conductors are selectively positioned in specific layers based on local requirements, allowing optimization of wiring resistance and cross-talk reduction in critical areas while maintaining overall IC functionality during scaling.
3Productivity
If routing conductors are positioned close together to reduce area, then routing efficiency improves, but coupling noise increases
Solution Approach 1:
The patent segments routing conductors into two distinct groups (first routing conductors and second routing conductors) that are spatially separated across different layers. This segmentation allows efficient routing through compact three-dimensional space while preventing coupling noise by ensuring physical separation between different signal types.
Solution Approach 2:
The patent utilizes the vertical dimension to separate routing conductors that would otherwise be close together in a planar arrangement. First routing conductors in a first layer and second routing conductors in a second layer can be positioned close together horizontally for routing efficiency while the vertical separation prevents coupling noise.
Data Source
AI summary
Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells having the word lines and high-voltage power lines positioned on one side of the transistors and the bit lines and low voltage power lines positioned on the other side of the transistor. The memory cells according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell.