9-Transistor SRAM Cell Architecture for Single-ADC In-Memory Computing
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Solution Overview
Problem
Existing compute-in-memory systems face challenges in efficiently performing multiply-accumulate operations and require multiple analog-to-digital conversions, leading to high power consumption and latency.
Innovation Solution
A 9-transistor SRAM-based memory cell with a controlled current source and switching transistor, allowing for simultaneous current summation and conversion to digital outputs using a single analog-to-digital converter, reducing the need for multiple conversions and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple analog-to-digital conversions are used in compute-in-memory systems, then computing accuracy is improved, but power consumption increases and latency increases
Solution Approach 1:
The patent combines multiple analog-to-digital conversions into a single parallel operation by designing a memory array where multiple memory cells share common readout lines. This allows simultaneous conversion of multiple analog signals (representing different weight values) into digital form using a single ADC, thereby maintaining computing accuracy while reducing power consumption and latency associated with sequential conversions
2Measurement precision
If multiple analog-to-digital conversions are used in compute-in-memory systems, then computing accuracy is improved, but latency increases
Solution Approach 1:
The patent merges multiple sequential analog-to-digital conversion operations into a single parallel operation. By configuring memory cells to share common readout lines and using a single ADC that can process multiple inputs simultaneously, the system achieves parallel conversion of multiple weight values, thereby reducing latency while maintaining the accuracy required for compute-in-memory operations
3Device complexity
If conventional SRAM cells are used for in-memory computing, then device simplicity is maintained, but multiply-accumulate operation efficiency is reduced
Solution Approach 1:
The patent extends the functionality of conventional SRAM cells by enabling them to perform both traditional memory storage operations and compute-in-memory multiply-accumulate operations. The memory cells are configured with controlled current sources and switching transistors that allow them to function as both storage elements and computational units, thereby maintaining device simplicity while improving productivity for MAC operations
Solution Approach 2:
The patent creates a simplified model of the memory cell structure that replicates the essential functionality of complex computational units while maintaining the simplicity of SRAM architecture. By using controlled current sources and switching transistors that can be integrated into standard SRAM cells, the design copies the computational capabilities of more complex devices without requiring fundamental structural changes, thus maintaining device simplicity while improving efficiency
Data Source
AI summary
An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.