SRAM Cell Two-Level Contacts for Low Aspect Ratio Manufacturing
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Solution Overview
Problem
Current semiconductor processes face challenges in forming SRAM cell structures with high aspect ratio contacts, which are difficult to manufacture due to shrinking feature sizes and increased contact resistance, leading to higher costs and reduced throughput, especially at advanced process nodes where multiple patterning steps are required.
Innovation Solution
The use of two-level contacts with reduced aspect ratios, allowing for single patterning photolithographic processes, and aggressive line end rules to form SRAM cell structures, which decreases contact resistance and increases packing density while reducing manufacturing costs by eliminating the need for double patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single patterning photolithographic process is used, then manufacturing cost is reduced and throughput is increased, but contact aspect ratio must be reduced
Solution Approach 1:
The patent transitions from vertical high aspect ratio contacts to horizontal low aspect ratio contacts by changing the orientation of the contact structure. This dimensional change allows single patterning to be used effectively while maintaining electrical connectivity, thereby increasing throughput without sacrificing manufacturing precision
Solution Approach 2:
The patent changes the aspect ratio parameter of the contacts from high to low, and modifies the contact geometry from vertical to horizontal orientation. These parameter changes enable the use of single patterning photolithography, reducing manufacturing complexity and increasing productivity
2Reliability
If multiple patterning steps are used, then contact resistance is reduced, but manufacturing cost increases and throughput decreases
Solution Approach 1:
By reorienting contacts from vertical to horizontal and reducing aspect ratio, the patent enables single patterning to achieve sufficient contact quality without multiple patterning steps, thereby reducing device complexity while maintaining acceptable contact resistance
Solution Approach 2:
The patent applies different contact geometries and orientations in different regions of the SRAM cell structure. Low aspect ratio horizontal contacts are used in specific locations where single patterning can effectively achieve low contact resistance, reducing the need for multiple patterning steps overall
3Area of moving object
If feature sizes are shrunk, then packing density is increased, but contact resistance increases and manufacturing difficulty increases
Solution Approach 1:
The patent compensates for feature size shrinkage by changing contact orientation from vertical to horizontal and reducing aspect ratio. This dimensional change maintains lower contact resistance despite smaller feature sizes, enabling increased packing density without sacrificing reliability
Solution Approach 2:
The patent employs composite contact structures combining through-silicon vias (TSVs) with horizontal low aspect ratio contacts. This composite approach addresses the challenges of feature size shrinkage by using multiple contact types with complementary characteristics, maintaining low contact resistance in scaled devices
4Ease of operation
If high aspect ratio contacts are used, then vertical connectivity is improved, but manufacturing difficulty increases and yield decreases
Solution Approach 1:
The patent reduces dependence on vertical connectivity by implementing horizontal low aspect ratio contacts. This dimensional change significantly eases manufacturing while maintaining electrical connectivity, thereby improving ease of manufacture and yield without completely sacrificing vertical connection functionality
Solution Approach 2:
The patent segments the contact function into multiple components: through-silicon vias for vertical connectivity and horizontal low aspect ratio contacts for lateral connectivity. This segmentation allows each contact type to be optimized for its specific function, with horizontal contacts easing manufacturing difficulty while TSVs provide necessary vertical connectivity
Data Source
AI summary
An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.