SRAM Cell Vertical Transistor Stacking for High Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SRAM cells based on vertical devices, such as vertical nanosheet or nanowire MOSFETs, face challenges in enhancing degree of integration and storage density, with no effective means to further improve these aspects.
Innovation Solution
The SRAM cell design involves vertically stacking transistors with pull-up, pull-down, and pass-gate transistors at different levels on a substrate, using a hard mask layer to define active regions and interconnection structures, allowing for self-aligned manufacturing and high mobility due to single-crystalline semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical devices are used to increase degree of integration, then storage density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements a stacked transistor architecture where multiple transistor layers are vertically nested within each other, with each layer containing pull-up, pull-down, and pass-gate transistors. This nesting approach allows six transistors to be integrated in a compact vertical footprint, significantly increasing storage density while managing manufacturing complexity through systematic layering
Solution Approach 2:
The patent transitions from planar 2D transistor arrangement to 3D vertical stacking, utilizing the vertical dimension to accommodate multiple transistor layers. This dimensional change enables higher integration by stacking transistors above each other rather than arranging them side-by-side, thereby increasing storage density without proportionally increasing footprint area
2Quantity of substance
If vertical nanosheet or nanowire MOSFETs are used, then degree of integration is improved, but effective means to further enhance integration are limited
Solution Approach 1:
The patent segments the SRAM cell into distinct functional layers: first and second pull-up transistor layers, first and second pull-down transistor layers, and pass-gate transistor layers. Each layer is independently structured with source/drain regions and channel regions, allowing systematic integration and future scalability while maintaining high degree of integration
Solution Approach 2:
The patent employs a flexible stacked transistor architecture that can be dynamically configured with different numbers and types of transistors in each layer. This dynamic structure allows future enhancement by adding more transistor layers or modifying existing ones, providing adaptability for further integration improvement
3Area of stationary object
If transistors are stacked at different levels, then footprint is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses a placeholder layer formed before the gate electrode layers that pre-defines the horizontal positions and footprints of the vertical transistors. This preliminary action establishes precise alignment references for subsequent manufacturing steps, ensuring accurate positioning of stacked transistors at different levels while reducing overall footprint
Solution Approach 2:
The placeholder layer acts as an intermediary element between the substrate and the gate electrode structures. It mediates the alignment process by providing a stable reference structure that facilitates precise positioning of multiple transistor layers, thereby reducing manufacturing precision requirements for direct alignment
Data Source
AI summary
A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.