SRAM Cell Footprint Reduction via Vertical Transistor Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the footprint of static random access memory (SRAM) cells to increase integration density, as current designs with vertical transistors have a large footprint, limiting the number of SRAM cells that can be integrated per unit area.
Innovation Solution
The design incorporates vertical transistors with a reduced footprint by forming pull-up and pull-down transistors and pass-gate transistors in stacked active levels, with self-aligned conductive traces and vias to reduce the overall size of the SRAM cell, allowing for increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistors are used in SRAM cell design, then integration density can be improved, but the footprint of each SRAM cell becomes large
Solution Approach 1:
The patent transitions from planar transistor layouts to vertical stacked transistor configurations, utilizing the third dimension (vertical stacking) to reduce the two-dimensional footprint of SRAM cells while maintaining functional integrity and improving integration density
Solution Approach 2:
The patent implements nested structures where conductive traces and vias are self-aligned within stacked transistor configurations, with lower-level traces and vias positioned beneath upper-level components, creating a compact nested arrangement that minimizes horizontal space occupation
2Productivity
If the footprint of SRAM cells is reduced to increase integration density, then more cells can be integrated per unit area, but manufacturing complexity increases
Solution Approach 1:
The patent employs self-aligned formation methods where conductive traces and vias are positioned and formed in advance with precise alignment to the stacked transistor structures, eliminating the need for complex post-fabrication alignment processes and reducing manufacturing complexity despite the reduced footprint
Solution Approach 2:
The patent divides the SRAM cell into distinct stacked functional blocks (pull-up transistors, pull-down transistors, pass-gate transistors) arranged vertically, with each segment having self-aligned conductive traces and vias, making the complex structure more manageable through modular segmentation
Data Source
AI summary
A method of forming an SRAM cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate transistor, and a second vertical pass-gate transistor over a semiconductor substrate. The method includes forming a first conductive trace over a top surface of the first vertical pull-down transistor and the first vertical pass-gate transistor, forming a second conductive trace over a top surface of the second vertical pull-down transistor and the second vertical pass-gate transistor, and forming a first vertical pull-up transistor over a first portion of the first conductive trace. The method also includes forming a second vertical pull-up transistor over a first portion of the second conductive trace. The method also includes forming a first via over the first conductive trace and forming a second via over the second conductive trace.