SRAM Write Margin Improvement via Dynamic Cell Voltage Control
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Solution Overview
Problem
The stability of SRAM write operations is compromised due to variations in transistor dimensions and stochastic doping fluctuations, leading to reduced write margins and unreliable performance, particularly in advanced CMOS processes where precise control of transistor thresholds is challenging.
Innovation Solution
The implementation of a tracking column with an identical structure to the normal column, coupled with a cell voltage control circuit and a cell voltage pull-down circuit, uses switches and a detector to reduce memory cell voltage during write operations, allowing precise control of voltage reduction and increasing the write margin without the complexity of prior art solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the transistor dimensions are varied or stochastic doping fluctuation occurs, then the transistor threshold varies, but the write margin is reduced
Solution Approach 1:
The patent changes the cell voltage parameter dynamically during write operations. By reducing the cell voltage below the word line turn-on voltage, the equivalent resistance of transistor PU increases, which reduces the voltage at node nv1 and improves the write margin, compensating for transistor threshold variations
2Reliability
If dual power supplies are used to reduce cell voltage during write operation, then the write margin is increased, but the circuit complexity and timing control difficulty increase
Solution Approach 1:
The patent extracts the voltage reduction function from complex dual power supply circuits and implements it through a simpler cell voltage pull-down circuit that operates independently during write operations, reducing circuit complexity while maintaining the write margin improvement
3Reliability
If floating column voltage is used to reduce cell voltage, then the write margin is improved, but the circuit is not suitable for too long memory cell columns due to excessive capacitance
Solution Approach 1:
The patent introduces a cell voltage pull-down circuit as an intermediary mechanism that actively controls the cell voltage reduction process. This mediator circuit compensates for the capacitance effects in long memory columns by providing controlled charge discharge paths, making the write margin improvement applicable to various column lengths
4Reliability
If charge sharing is used to reduce cell voltage, then the write margin is increased, but the voltage reduction accuracy is hard to control due to capacitance ratio variations
Solution Approach 1:
The patent implements feedback control through the detector and switch mechanism. The detector monitors the cell voltage and provides feedback to control the pull-down switch timing, ensuring accurate voltage reduction to the predetermined level regardless of capacitance variations, thereby improving voltage reduction precision
Data Source
AI summary
An SRAM and a forming method and a controlling method thereof are provided. The above-mentioned SRAM includes a tracking column, a normal column, a cell voltage control circuit and a cell voltage pull-down circuit. Each of the tracking column and the normal column includes a plurality of memory cells. The cell voltage control circuit is coupled to the tracking column and the normal column for connecting an operation voltage to the two columns before a write operation of the SRAM starts and for disconnecting the operation voltage from the two columns after the write operation starts. The cell voltage pull-down circuit is coupled to the two columns for pulling down the cell voltages of the two columns after the write operation starts and for ceasing pulling down the cell voltage of the normal column when the cell voltage of the tracking column drops down to a predetermined voltage.