SRAM Memory Cell Layout With Fewer Wiring Layers
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Solution Overview
Problem
Current SRAM memory cells with CMOS inverter circuits face challenges in reducing the area occupied and the number of wiring layers, which hinders high integration and efficiency.
Innovation Solution
The proposed memory cell design incorporates a flip-flop circuit with two CMOS inverter circuits and transfer transistors, where transistors are stacked with gate electrode layers, and drain and source regions are connected in specific configurations to reduce area and wiring layers, utilizing a substrate with high concentration impurity regions or conductive material layers for connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate electrode wiring is formed in vertical and horizontal directions only, then ease of manufacture is improved, but area of the memory cell increases
Solution Approach 1:
The patent introduces oblique direction wiring (gate electrode wiring extending in directions other than purely vertical or horizontal) to reduce memory cell area. This dimensional change in wiring orientation allows for more compact layout while remaining manufacturable with appropriate process techniques.
2Adaptability or versatility
If four wiring layers are provided for word line, bit lines, and power supply lines, then connectivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple wiring functions into fewer layers by using oblique direction wiring to achieve connectivity that would otherwise require separate layers. Specifically, the gate electrode wiring in oblique directions provides both gate control and power supply connectivity, reducing the total number of wiring layers from four to three.
3Area of moving object
If transistors are stacked with gate electrode layers, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the transistor structure into stacked components (channel formation regions at different heights) with gate electrode layers controlling each segment. This vertical segmentation reduces planar area while the segmentation itself helps manage manufacturing precision by allowing independent formation and alignment of each stacked component.
Data Source
AI summary
A memory cell includes a flip-flop circuit that includes a first CMOS inverter circuit including a 1Ath transistor TR1 and a 1Bth transistor TR2 and a second inverter circuit including a 2Ath transistor TR3 and a 2Bth transistor TR4 and two transfer transistors TR5 and TR6. The 1Ath transistor TR1 and the 2Ath transistor TR2 are connected to a common first power supply line, and the 1Bth transistor TR3 and the 2Bth transistor TR4 are connected to a common second power supply line.