SRAM Cell Parasitic Reduction via Multi-Layer Word-Line Segmentation
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Solution Overview
Problem
As SRAM cells scale down, increasing sheet resistance of metal lines leads to higher RC delay, reducing read and write speeds, and the larger size of split-word-line SRAM cells results in higher bit-line metal coupling capacitance and worsened resistance, hindering speed improvements.
Innovation Solution
The implementation of short CVss landing pads and double word-lines with increased thickness in specific metal layers reduces parasitic capacitance and resistance, allowing for reduced RC delay and improved SRAM cell speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If SRAM cells are down-scaled, then area is reduced, but sheet resistance of metal lines increases leading to higher RC delay
Solution Approach 1:
The patent introduces a dual-layer metal interconnect structure where word-lines are formed in both the first metal layer and the second metal layer. This three-dimensional arrangement allows current to flow through multiple parallel paths, effectively reducing the RC delay by distributing the electrical load across different spatial dimensions while maintaining compact cell area.
Solution Approach 2:
The word-line is segmented into multiple sections across different metal layers. Specifically, the first word-line is formed in the first metal layer and a second word-line is formed in the second metal layer, creating parallel conduction paths that reduce the overall resistance and capacitance of the word-line structure.
2Speed
If split-word-line SRAM cells are used, then bit-line length is reduced, but cell size increases leading to higher bit-line metal coupling capacitance
Solution Approach 1:
The patent employs a multi-layer metal structure where bit-lines are formed in the first metal layer and word-lines are formed in both the first and second metal layers. This vertical stacking allows shorter bit-line connections while maintaining proper electrical isolation, reducing coupling capacitance between bit-lines and word-lines despite larger cell footprint.
Solution Approach 2:
The second metal layer acts as an intermediary structure that carries additional word-line connections. This intermediate layer provides alternative routing paths that reduce the coupling capacitance between bit-lines and word-lines by increasing spatial separation while maintaining electrical connectivity.
3Adaptability or versatility
If word-lines are extended to connect more columns, then cell coverage is increased, but resistance increases
Solution Approach 1:
The word-line is divided into multiple segments distributed across different metal layers. The first word-line in the first metal layer and the second word-line in the second metal layer create parallel conduction paths, effectively segmenting the current flow to reduce overall resistance while maintaining extended coverage across multiple columns.
Solution Approach 2:
The patent merges multiple word-line paths by forming conductive structures in both the first and second metal layers that connect to the same storage nodes. This combining of parallel paths reduces the effective resistance by providing multiple current flow routes across the extended word-line coverage area.
Data Source
AI summary
A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.