SRAM Bit Cell Channel Depopulation for Read-Write Balance
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is compounded by the trade-off between feature dimension and spacing constraints in lithographic processes.
Innovation Solution
The implementation of nanoribbon and nanowire transistors with depopulated channels, achieved through top-down and bottom-up channel depopulation processes, allows for modulation of drive currents by selectively rendering discrete nanowire channels non-conducting, thereby optimizing performance in integrated circuits like SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to increase density, then the number of memory or logic devices per chip increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar transistors to vertically-oriented nanowire transistors with multiple channels stacked in the vertical dimension. This dimensional change allows continued scaling and density improvement while maintaining effective gate control through the multi-gate structure that wraps around each nanowire channel.
Solution Approach 2:
The patent divides the channel into multiple discrete nanowire channels stacked vertically, with selective depopulation of specific channels. This segmentation allows independent control of drive current through each channel, enabling optimization of both density and short channel control by activating only the necessary number of channels.
2Productivity
If feature size is reduced to increase device density, then more devices fit on chip, but lithographic process constraints between critical dimension and spacing become overwhelming
Solution Approach 1:
By moving to vertical nanowire channels stacked in the third dimension, the patent reduces the lithographic footprint on the chip plane. The critical dimension becomes the nanowire width which can be controlled by epitaxial growth rather than lithography, while spacing constraints are relaxed as channels are separated vertically rather than laterally.
Solution Approach 2:
The patent replaces lithographic patterning of channels with epitaxial growth of alternating semiconductor layers that are subsequently released to form suspended nanowires. This substitution of manufacturing mechanism avoids the lithographic resolution limits that constrain feature size and spacing.
3Power
If all nanowire channels are kept active to maximize drive current, then transistor performance improves, but read stability and write-ability balance in SRAM requires assist circuits that increase chip area and power consumption
Solution Approach 1:
The patent applies different states to different parts of the channel structure by selectively depopulating specific nanowire channels while maintaining others as active channels. This local differentiation allows precise control of drive current to achieve the required balance between read stability and write-ability without assist circuits, reducing both chip area and power consumption.
Solution Approach 2:
The patent changes the physical state of selected nanowire channels from conductive to non-conductive through depopulation, effectively modulating the drive current parameter. This parameter control enables optimization of SRAM cell performance without requiring additional assist circuitry.
Data Source
AI summary
Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.