SRAM Characteristic Measuring Circuit for Transistor Variation
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Solution Overview
Problem
The miniaturization of transistors in semiconductor integrated circuits leads to increased variation in transistor characteristics, making it difficult to satisfy the contradictory conditions for SRAM memory cell performance, particularly due to the complexity and additional processing steps required for measuring transistor characteristics.
Innovation Solution
Incorporating a characteristic measuring circuit with transistors configured similarly to those in SRAM memory cells, allowing for external estimation of SRAM memory cell characteristics through a terminal, which reduces measurement errors and enables circuit modifications for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors are miniaturized to reduce chip area and cost, then chip area and cost are reduced, but transistor characteristic variation increases
Solution Approach 1:
The patent applies preliminary action by measuring transistor characteristics during the fabrication process itself, before the chip is completed. This allows early detection and compensation of characteristic variations, enabling corrective actions to be taken while the manufacturing process is still ongoing, thus mitigating the impact of miniaturization-induced variation.
Solution Approach 2:
The patent implements feedback by using measured transistor characteristics to adjust subsequent fabrication parameters or circuit design. The measurement results feed back into the manufacturing process, allowing real-time optimization and compensation for the increased variation caused by transistor miniaturization, thereby maintaining manufacturing precision despite smaller feature sizes.
2Measurement precision
If probe pads are provided on the chip for measuring transistor characteristics, then measurement capability is improved, but fabrication process complexity increases and additional processing steps are required
Solution Approach 1:
The patent applies universality by designing measurement circuits that can measure multiple transistor characteristics (threshold voltage, on-current, etc.) using the same physical structure and access points. This multi-functional approach eliminates the need for separate probe pads for each measurement type, reducing fabrication complexity while maintaining comprehensive measurement capability.
Solution Approach 2:
The patent merges the measurement function with the existing transistor structure and circuit elements. Instead of adding separate probe pads and measurement infrastructure, the measurement capability is integrated into the transistor terminals and existing circuit nodes, combining multiple functions (memory operation and characteristic measurement) into a unified structure that reduces overall device complexity.
3Productivity
If transistor size is reduced to increase the number of transistors on a chip, then transistor density and integration are improved, but the number of transistors mounted increases causing greater variation effects
Solution Approach 1:
The patent applies preliminary action by implementing measurement and compensation mechanisms during the fabrication process itself, before all transistors are completed. This allows early identification of variation trends across the chip, enabling proactive adjustments to be made while manufacturing is ongoing, thus maintaining precision despite high transistor density.
Solution Approach 2:
The patent implements feedback loops that use measurement data from transistors to adjust fabrication parameters or circuit characteristics in real-time. This feedback mechanism compensates for the cumulative variation effects that arise from having many transistors on a single chip, maintaining manufacturing precision despite increased transistor density and the resulting greater variation impacts.
Data Source
AI summary
A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.