SRAM Charge Recycling Circuit for Low Power Write Operations
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Solution Overview
Problem
Integrated circuit memory devices face challenges in reducing energy consumption and parasitic elements' influence, particularly in SRAM devices, due to reduced power supply voltage and increased operating speed, which affects performance and efficiency.
Innovation Solution
An SRAM device with a charge storage circuit and switching controller that selectively blocks connections between memory cells and ground, allowing charge sharing between bit lines, and using write assist transistors to manage charge transfer during write operations, thereby reducing energy consumption and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply voltage is reduced to lower power consumption, then energy consumption decreases, but the influence of parasitic elements increases and performance deteriorates
Solution Approach 1:
The charge storage node precharges bit lines before write operations by accumulating charge from previously accessed bit lines. This preliminary charge accumulation reduces the voltage swing required during write operations, enabling the circuit to operate reliably at lower supply voltages while maintaining performance
Solution Approach 2:
The invention changes the voltage parameter dynamics by using a charge storage node that can hold and transfer charge, creating variable voltage conditions on bit lines. This allows the system to operate with reduced supply voltage by dynamically adjusting bit line voltages through charge transfer rather than relying on high static supply voltage
2Productivity
If operating speed is increased, then productivity improves, but the influence of parasitic elements increases and energy consumption increases
Solution Approach 1:
The charge storage node performs preliminary charge accumulation during non-critical time periods, preparing bit lines for future write operations. This allows faster write operations when needed without requiring continuous high energy input, as the charge is already prepared and stored
Solution Approach 2:
The charge storage node continuously accumulates charge from bit lines during read operations and idle periods, maintaining a ready supply of charge for subsequent write operations. This continuous charge accumulation enables high-speed operation without proportional increases in energy consumption
3Area of moving object
If wiring line dimensions are reduced for high integration, then device density improves, but parasitic elements increase and performance deteriorates
Solution Approach 1:
The charge storage node acts as an intermediary between bit lines and memory cells, buffering charge transfers and isolating the impact of parasitic elements in reduced-dimension wiring. This intermediary structure compensates for the increased parasitic effects caused by smaller wiring dimensions
Data Source
AI summary
An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.