SRAM Compute-in-Memory Charge Sharing for Accurate MAC
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Solution Overview
Problem
Conventional SRAM-based compute-in-memory (CIM) designs suffer from inaccuracies due to cell current variations during multiply-accumulate (MAC) operations, leading to inaccuracies in memory array computations.
Innovation Solution
Implement a charge sharing scheme among capacitors associated with each SRAM cell in a column to average the read bitline (RBL) current, using a capacitor to store product signals and a switch device to transfer charge to the RBL, thereby mitigating cell current variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SRAM-based CIM designs are used to perform MAC operations, then computation speed is improved by performing calculations at memory cell level, but computation accuracy deteriorates due to cell current variations
Solution Approach 1:
A capacitor is introduced as an intermediary element between the storage element and the read bitline. The capacitor captures and holds the product signal charge during the computation process, isolating the read bitline from direct exposure to cell current variations. This intermediary mechanism allows accurate charge accumulation while maintaining fast computation speeds inherent to SRAM-based CIM architectures
Solution Approach 2:
The invention changes the operational parameter from direct current-based computation to charge-based computation. By converting the product signal into an electrical charge stored on a capacitor, the system transforms the nature of the computation medium. This parameter change makes the computation immune to cell current variations while preserving the speed advantages of SRAM-based implementation
2Measurement precision
If charge sharing scheme is implemented among capacitors to average RBL current, then computation accuracy is improved, but device complexity increases
Solution Approach 1:
Multiple capacitors associated with different storage elements in the same column are merged through charge sharing on the common read bitline. The charges from individual capacitors are combined and averaged, naturally canceling out cell current variations. This merging approach achieves accuracy improvement without requiring complex external control circuits, as the charge sharing occurs inherently through the shared bitline architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of CIM computations by averaging cell currents, resulting in improved precision and reliability of MAC operations.
Implementation Method 1
a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal
Implementation Method 2
a second switch device adapted to transfer the charge on the capacitor to the RBL
Data Source
AI summary
A charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for CIM computing. In some embodiments, a capacitor is associated with each SRAM cell, and the capacitors associated with all SRAM cells in a column are included in averaging the RBL current. In some embodiments, a memory unit associated to an RBL in a CIM device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.