SRAM Defective Column Replacement with Load Isolation
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Solution Overview
Problem
The challenge in SRAM memory design is to increase density while minimizing defects and their associated energy consumption and access time, as scaling down semiconductor structures tightens manufacturing tolerances and increases the likelihood of defects, leading to higher energy costs and decreased reliability.
Innovation Solution
The method involves replacing a group of defective memory cells with a redundant group by rerouting the signal path and isolating the load imposed by the defective cells, using control circuits to shift functionality from faulty columns to spare columns and isolate the load, thereby reducing the operational burden on driver circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spare cells are incorporated into memory to substitute defective cells, then yield is increased, but current load increases and access time increases
Solution Approach 1:
The patent extracts the defective column from the active memory array by isolating it through a transmission gate. The defective column is effectively removed from the signal path while maintaining its physical presence in the array, allowing spare columns to take over its functionality without carrying the defective column's load.
Solution Approach 2:
The transmission gate acts as an intermediary element that selectively connects or disconnects the defective column from the bit lines. By controlling the transmission gate's state, the system can route signals away from defective columns and toward spare columns, mediating between the defective array and the functional spare resources.
2Reliability
If spare cells are incorporated into memory to substitute defective cells, then yield is increased, but energy consumption increases
Solution Approach 1:
The patent extracts the defective column from the active memory array by isolating it through a transmission gate. The defective column is effectively removed from the signal path while maintaining its physical presence in the array, allowing spare columns to take over its functionality without carrying the defective column's load.
Solution Approach 2:
The system dynamically reconfigures the memory array by using control signals to activate different transmission gates based on which columns are defective. This dynamic switching allows the memory to adapt its operational configuration, enabling spare columns to replace defective ones on-the-fly without physical restructuring.
3Quantity of substance
If dimensions of semiconductor structures are decreased to increase density, then memory density is increased, but manufacturing precision deteriorates
Solution Approach 1:
The patent changes the operational parameters of the memory by introducing isolation mechanisms (transmission gates) that allow defective columns to be electrically disconnected. This parameter change enables the system to tolerate manufacturing variations and defects that would otherwise render the high-density array non-functional.
Solution Approach 2:
The patent segments the memory array into independently controllable columns, each with its own isolation transmission gate. This segmentation allows individual defective columns to be isolated without affecting the operation of other columns, thereby maintaining the functionality of the high-density array despite manufacturing defects.
Data Source
AI summary
Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.