SRAM Column Sleep Circuits With Wake Pre-Charge for Low Leakage
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Solution Overview
Problem
The increasing leakage current in semiconductor chips due to reduced transistor threshold voltages leads to higher power consumption, necessitating costly cooling systems and design inefficiencies, particularly in integrated circuits with SRAM memory arrays.
Innovation Solution
Implementing wake pre-charge circuitry in SRAM memory arrays to pre-charge bit lines to an idle voltage level (VDD−Vt) during idle states, reducing leakage current and minimizing transition latency to active states by using p-type transistors and keeper circuitry to maintain voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor channel length is reduced to increase functionality and performance, then more functionality and performance are achieved while consuming less space, but threshold voltage decreases causing increased leakage current
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to an intermediate voltage level (VDD - Vt) before actual memory access operations. This pre-charging state is maintained during idle periods using wake pre-charge circuitry, which proactively prepares the bit lines for future access without requiring full charging to VDD, thereby reducing leakage current while maintaining readiness for rapid access.
2Use of energy by stationary object
If transistors are disabled to reduce power consumption, then power consumption decreases, but off-state current still flows due to small threshold voltage
Solution Approach 1:
The patent applies parameter changes by modifying the voltage level on bit lines from the traditional binary states (0V or VDD) to an intermediate voltage state (VDD - Vt). This parameter change reduces the voltage differential across disabled transistors, thereby minimizing off-state leakage current while maintaining the ability to rapidly transition to active states when needed.
3Loss of energy
If bit lines are fully pre-charged to VDD during idle states, then leakage current is reduced, but transition latency increases when transitioning to active state
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to an intermediate voltage level (VDD - Vt) during idle states, which is sufficient to reduce leakage current without requiring full charging to VDD. When transitioning to an active state, only a small additional voltage increment is needed, significantly reducing transition latency compared to charging from a fully discharged state.
Solution Approach 2:
The patent applies parameter changes by using an intermediate voltage level (VDD - Vt) instead of the traditional full VDD level for pre-charged bit lines. This parameter optimization reduces the voltage differential that needs to be charged during active transitions, thereby minimizing transition latency while maintaining low leakage current during idle states.
Data Source
AI summary
An apparatus and method for efficiently designing memory arrays in semiconductor dies. In various implementations, a memory array utilizes wake pre-charge circuitry to reduce both leakage current and a transition from an idle state. When control circuitry of the memory array determines that there are no upcoming memory accesses, it disables bit line pre-charge circuitry of columns of the array. The control circuitry enables wake pre-charge circuitry to charge the bit lines to an idle voltage level equal to a difference between the power supply voltage level and a threshold voltage of a transistor. When the control circuitry determines a memory access is pending, the control circuitry transitions the memory array to an active state. Both the amount of voltage difference and the resulting latency to charge the bit lines from the idle voltage level to the power supply reference voltage level are small.