SRAM Semiconductor Layout With Conductive Channel Word Lines
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Solution Overview
Problem
Current semiconductor structures face challenges in reducing wiring space and resistance in word lines, which affects the conduction rate and delay in semiconductor structures, particularly in SRAM units.
Innovation Solution
A semiconductor structure with a first conductive channel located between adjacent second active regions, electrically connecting second source regions, and a manufacturing method that includes forming this channel to reduce wiring space and improve layout for word lines, thereby reducing resistance and enhancing signal transfer capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional wiring layout is used in SRAM structures, then wiring space is sufficient, but wiring space is excessive and resistance is high
Solution Approach 1:
The conductive channel is formed within the substrate plane rather than using vertical interconnects or surface wiring, utilizing the lateral dimension of the substrate to reduce wiring length and improve conduction efficiency
Solution Approach 2:
The conductive channel merges the functions of substrate interconnection and transistor source/drain region connection, eliminating the need for separate wiring layers and reducing overall wiring space
2Area of stationary object
If conventional word line layout is used, then layout simplicity is maintained, but layout space is excessive and delay is increased
Solution Approach 1:
The word line is segmented into multiple sections with different conductive channel configurations, allowing optimization of each segment for speed while reducing overall layout space requirements
Solution Approach 2:
Different regions of the substrate are configured with different conductive channel properties to optimize local conduction paths, reducing delay in critical paths while maintaining overall layout efficiency
Data Source
AI summary
Embodiments of the present disclosure relate to the semiconductor field, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, first gates and second gates, and a first conductive channel; where the substrate includes first active regions and two second active regions located between adjacent first active regions, the first active region defines a pull-down transistor, the second active region defines a pull-up transistor; the first active region has a first source region, a first channel region, and a first drain region arranged along a second direction.