SRAM Contact Plug Architecture for Exposure Quality
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Solution Overview
Problem
Current SRAM architectures face challenges in producing desirable patterns as the exposure process pitch decreases, leading to difficulties in enhancing exposure quality.
Innovation Solution
The SRAM design incorporates two interlayer dielectric (ILD) layers with a first contact plug disposed within the bottom ILD layer, electrically connecting to the drains of multiple transistors, eliminating the need for additional contact plugs above it, thereby reducing pattern density and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SRAM architecture with multiple contact plugs is used, then electrical connectivity is achieved, but pattern density increases leading to poor exposure quality
Solution Approach 1:
The patent extracts unnecessary contact plugs from the conventional SRAM architecture. Specifically, it removes redundant contact plugs in the upper ILD layer by implementing a shared contact plug structure where a single contact plug in the bottom ILD layer serves multiple transistors, thereby reducing overall pattern density and improving exposure quality
Solution Approach 2:
The patent applies multi-functionality by designing a single contact plug structure that performs multiple electrical connection functions. The shared contact plug in the bottom ILD layer simultaneously connects to drains of multiple transistors (pull-up, pull-down, and access transistors), eliminating the need for separate contact plugs for each transistor and reducing pattern complexity
2Reliability
If multiple contact plugs are disposed in upper ILD layer, then electrical connectivity is achieved, but manufacturing yield decreases due to increased shorting risk
Solution Approach 1:
The patent extracts redundant contact plugs from the upper ILD layer configuration. By removing these unnecessary contact plugs and implementing a shared contact plug structure in the bottom ILD layer, the design reduces the number of potential failure points and minimizes the risk of shorting between adjacent contact plugs, thereby improving manufacturing yield
Solution Approach 2:
The patent converts the potential harm of complex contact plug arrangements into a benefit by using a simplified shared contact plug structure. This configuration not only reduces shorting risk but also improves electrical performance by reducing parasitic capacitance and resistance associated with multiple stacked contact plugs
Data Source
AI summary
A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.