SRAM Control Circuit Voltage Boosting for Write Reliability
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Solution Overview
Problem
Conventional SRAM designs face challenges with low write ability, high power consumption, and risk of gate oxidization layer penetration due to the need for additional transistors in memory cells, which affects efficiency and manufacturing costs.
Innovation Solution
A control circuit for SRAM comprising a memory array, a word-line driver, a boost circuit, and a voltage level detecting circuit that adjusts the operating voltage by activating or shutting down the boost circuit based on detected voltage levels, preventing excessive voltage that could damage the gate oxidization layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more transistors are used to improve write ability in SRAM, then the write ability is improved, but the unit capacity decreases and power consumption increases
Solution Approach 1:
The patent changes the operating voltage parameter dynamically. When the supply voltage is low, the boost circuit activates to provide a higher voltage for writing operations, improving write ability without requiring additional transistors. This resolves the contradiction by improving write ability through voltage optimization rather than increasing transistor count, thereby maintaining unit capacity.
Solution Approach 2:
The patent introduces a dynamic voltage adjustment mechanism where the boost circuit is activated only when needed (when supply voltage is below a threshold). This dynamic approach allows the system to adapt to different operating conditions, improving write ability when required while maintaining normal operation characteristics otherwise, thus avoiding the need for permanent additional transistors.
2Reliability
If word-line boost circuits are used to improve write ability, then the write ability is improved, but the gate oxidization layer is prone to penetration
Solution Approach 1:
The patent incorporates a voltage detection mechanism that monitors the supply voltage level and provides feedback to control the boost circuit activation. The boost circuit is activated only when the supply voltage is below a predetermined threshold, preventing excessive voltage that could penetrate the gate oxidization layer. This feedback control resolves the contradiction by enabling write ability improvement while protecting against voltage-induced damage.
Solution Approach 2:
The patent uses dynamic voltage boosting that activates only when the supply voltage is insufficient. The boost circuit provides additional voltage temporarily during writing operations and then deactivates, preventing continuous high voltage that could damage the gate oxidization layer. This dynamic approach improves write ability while minimizing harmful voltage effects.
3Productivity
If the boost circuit is always activated to provide higher voltage, then the operating efficiency is improved, but the gate oxidization layer may be penetrated due to excessive voltage
Solution Approach 1:
The patent implements a voltage-level detecting circuit that continuously monitors the supply voltage and provides feedback to control the boost circuit. The boost circuit is activated only when the supply voltage is below a predetermined threshold, ensuring that higher voltage is provided only when needed for efficient operation. This feedback mechanism prevents excessive voltage that could penetrate the gate oxidization layer, thus resolving the contradiction between operating efficiency and device protection.
Solution Approach 2:
The patent dynamically changes the operating voltage parameter based on supply voltage conditions. When the supply voltage is low, the boost circuit activates to provide higher voltage for efficient operation. When the supply voltage is sufficient, the boost circuit remains inactive, preventing excessive voltage. This parameter optimization improves operating efficiency while protecting against voltage-induced damage to the gate oxidization layer.
Data Source
AI summary
A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.