SRAM Memory Cell with Counter-Electrode Stability
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Solution Overview
Problem
Conventional SRAM memory cells with four transistors are not sufficiently stable due to variations in transistor electric performances and temperature sensitivity, leading to increased complexity and reduced surface area gains when trying to reduce the number of transistors for more compact designs.
Innovation Solution
A compact SRAM memory cell design featuring two pairs of transistors connected in series, with counter-electrodes overlapping semiconductor active areas, allowing for a more compact layout without increasing fabrication complexity, by using semiconductor-on-insulator transistors and optimizing transistor placement and gate connections to reduce stray capacitances and improve stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of transistors is reduced to four for compact design, then the surface area is reduced, but the stability and operation ruggedness deteriorate due to variations in transistor electric performances and temperature sensitivity
Solution Approach 1:
The patent introduces a dual-gate transistor structure where a second gate electrode is added beneath the first gate electrode, creating a vertical stacking arrangement. This dimensional change allows the transistor to be controlled from both top and bottom, improving stability without increasing lateral surface area. The counter-electrode is positioned in the substrate below the transistor, forming a vertical field effect that enhances control over the channel without occupying additional planar space.
Solution Approach 2:
The patent modifies the electrical parameters of the transistor by adding a counter-electrode in the substrate that can be independently biased. This allows dynamic adjustment of the threshold voltage and electric field distribution within the transistor channel, compensating for process variations and temperature effects. The counter-electrode creates an additional degree of freedom in controlling the transistor's electrical characteristics, improving operation ruggedness while maintaining the compact four-transistor cell structure.
2Reliability
If dual-gate transistors with counter-electrodes are used to improve electric behavior, then the stability and performance are improved, but the fabrication complexity increases due to the presence of four counter-electrodes
Solution Approach 1:
The patent merges the counter-electrode function with the substrate structure itself. Rather than adding separate counter-electrode components, the substrate is doped or metallized to directly form the counter-electrode regions. This integration reduces the number of discrete fabrication steps and eliminates the need for additional alignment and patterning processes that would be required for separate counter-electrode structures.
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support, electrical isolation through the insulating layer, and acts as the counter-electrode when doped or metallized. This multi-functionality reduces the overall device complexity by eliminating dedicated counter-electrode structures and their associated fabrication processes, while still achieving the desired electrical control.
3Reliability
If conventional six-transistor SRAM cell is used, then the operation stability is maintained, but the surface area occupied is too large for compact integrated circuits
Solution Approach 1:
The patent transitions from a planar six-transistor layout to a vertical dual-gate transistor structure. By stacking gate electrodes and utilizing the substrate depth for the counter-electrode, the design achieves enhanced stability control within a reduced lateral footprint. The vertical field effect from the counter-electrode provides additional control without requiring the extra transistors that would occupy additional planar space in a conventional cell.
Solution Approach 2:
The patent extracts the load transistor function from the conventional six-transistor SRAM cell, eliminating the need for dedicated load transistors. The dual-gate transistor structure with counter-electrode control inherently provides the load function through its enhanced voltage control capability, reducing the transistor count from six to four while maintaining stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a more compact and stable SRAM memory cell with improved electric performance, reducing the need for additional compensation circuits and simplifying the fabrication process, while maintaining the advantages of dual-gate transistors.
Implementation Method 1
a support substrate with first and second counter-electrodes, the first and second counter-electrodes being located respectively overlapping the first and second areas made from semiconductor material
Data Source
AI summary
The memory cell is of SRAM type with four transistors provided with a counter-electrode. It comprises a first area made from semiconductor material with a first transfer transistor and a first driver transistor connected in series, their common terminal defining a first electric node. A second transfer transistor and a second driver transistor are connected in series on a second area made from semiconductor material and their common terminal defines a second electric node. The support substrate comprises first and second counter-electrodes. The first and second counter-electrodes are located respectively facing the first and second semiconductor material areas. The first transfer transistor and second driver transistor are on a first side of a plane passing through the first and second electric nodes whereas the first driver transistor and second transfer transistor are on the other side of the plane.