SRAM Arrays for Crash Data Retention During Global Reset
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Solution Overview
Problem
Current systems face challenges in reliably harvesting crash data from system-on-a-chip (SOC) or system-on-a-package (SOP) platforms due to instability before a global reset, leading to loss of critical error information and increased downtime, especially when trying to retrieve and store crash log data after a catastrophic error.
Innovation Solution
Incorporating static random access memory (SRAM) arrays at each die of the SOC or SOP that remain powered during a global reset, allowing crash log agents to save and maintain error information without re-initialization, thus eliminating the need for external non-volatile memory and reducing complexities associated with sticky registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If crash log agents use external non-volatile memory to store error information, then data persistence is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error information storage function from external non-volatile memory and relocates it to internal SRAM arrays at each die. This eliminates the need for external memory components and simplifies the overall device architecture while maintaining data persistence through the always-on power rail.
Solution Approach 2:
The SRAM arrays serve multiple functions: they store crash log error information, persist through global resets, and are accessible to crash log agents without requiring external memory interfaces. This multi-functionality reduces device complexity by consolidating storage capabilities within the existing die structure.
2Reliability
If the system performs a global reset to recover from catastrophic errors, then system reliability is improved, but loss of error information occurs
Solution Approach 1:
The patent implements beforehand cushioning by maintaining SRAM arrays that are powered continuously through the global reset process. These arrays act as a cushion that preserves error information during the reset operation, ensuring that critical crash log data is not lost even though the system is undergoing a reliability-restoring reset cycle.
Solution Approach 2:
The SRAM arrays serve as an intermediary between the volatile memory that loses data during reset and the persistent storage need. They maintain error information throughout the global reset process, acting as a mediator that bridges the contradiction between system reliability recovery and information preservation.
3Stability of the object's composition
If crash log agents re-initialize after a global reset, then system state is restored, but error information is lost
Solution Approach 1:
The patent applies preliminary action by having crash log agents write error information to SRAM arrays before the global reset occurs. This preliminary storage ensures that when agents re-initialize after the reset, their error information is already preserved in the always-on powered SRAM, eliminating the need for complex re-initialization procedures that would normally result in data loss.
4Reliability
If external non-volatile memory is used for crash data storage, then data retention is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the crash log storage function with the existing SRAM array infrastructure at each die. Instead of adding separate external non-volatile memory components, the solution combines error information retention capabilities into the existing on-die SRAM structure, simplifying manufacturing by eliminating additional external components and interconnects.
Data Source
AI summary
Examples include techniques to collecting and providing error related information for a multi-die system-on-a-chip (SOC) computing system following a critical or catastrophic error. Examples include circuitry on a first die that is configured to receive an indication of a critical or catastrophic error and cause error related information to be stored to a volatile memory at the first die that is arranged to continually maintain power during a global reset of the SOC. The circuitry can also be configured to provide the stored error related information to a requestor following the global reset of the SOC.