SRAM Dynamic Failure Handling Using CRC and Address Remapping
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Solution Overview
Problem
Existing SRAM failure handling systems are limited in their ability to dynamically handle failures that occur during the operation of SRAM after initial failure handling has been completed, as they primarily focus on hard fault detection under worst-case conditions and do not account for failures caused by impurities, usage, or external factors like electrostatic discharge.
Innovation Solution
An SRAM dynamic failure handling system that utilizes a cyclic redundancy check (CRC) to identify and remap fault addresses in real-time, using a frame memory with separate real and spare address areas, a write controller, a read controller, and a failure handler to dynamically manage failures by mapping fault addresses to spare addresses, enabling continuous operation even after initial failure handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BIST and BISR are performed to handle SRAM failures, then initial hard faults can be detected and repaired, but additional failures occurring during operation cannot be handled
Solution Approach 1:
The patent implements continuous feedback through CRC checking of read data during SRAM operation. When data is read from SRAM, a CRC check is performed to verify integrity. If a CRC error is detected, the system generates an error flag and dynamically remaps the fault address to a spare address, enabling ongoing failure detection and handling beyond initial BIST
Solution Approach 2:
The system transitions from static failure handling (BIST/BISR performed once under worst-case conditions) to dynamic failure handling that operates continuously during SRAM usage. The CRC checking and address remapping occur in real-time based on actual operational conditions, allowing the system to adapt to failures as they occur during normal operation
2Measurement precision
If test is performed mainly for hard fault detection under worst conditions, then initial failures can be identified, but failures caused by impurities, usage, or external factors cannot be detected
Solution Approach 1:
The CRC checking mechanism serves multiple functions: it detects hard faults, soft errors, and failures caused by various factors (impurities, usage, ESD) using a single continuous verification process. This universal error detection approach covers all failure modes without requiring separate test procedures for each type of failure
3Reliability
If BIST patterns and addresses are generated and compared to detect failures, then hard faults can be identified, but continuous monitoring during operation is not achieved
Solution Approach 1:
The system performs continuous CRC checking on every data read from SRAM during normal operation, eliminating the gap between initial BIST and ongoing usage. This continuous monitoring ensures failures are detected immediately when they occur, rather than waiting for periodic re-testing or end-of-life evaluation
Data Source
AI summary
A method for dynamically handling the failure of the static random-access memory (SRAM) dynamic failure handling system using a cyclic redundancy check (CRC) includes obtaining a write data; determining a write address; storing the write data at the write address of a frame memory which is composed of the SRAM and includes a real address area and a spare address area which are distinguished from each other; storing, in response to the write address, a write cyclic redundancy check (CRC) generated by performing a CRC calculation on the write data; determining a read address; reading a read data from the read address of the frame memory; determining whether, based on the A CRC remainder W_CRC corresponding to the read address and the read data, a CRC error occurs, and generating an error flag when the CRC error occurs; determining a fault address based on the error flag; and mapping the fault address to one of non-fault spare addresses of the spare address area when the fault address is an address of the real address area.