SRAM-Based Cryptographic Key Generation Using Biased Initialization
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Solution Overview
Problem
Existing methods for generating cryptographic keys from SRAM memory are inefficient, requiring a lengthy enrolment phase, significant memory space, and often necessitate the use of non-volatile memory and error correction codes.
Innovation Solution
A method involving biased initializations of SRAM memory cells in two distinct regions to quickly identify highly biased bits, which are then used to form a digital key, reducing the need for extensive enrolment phases and minimizing memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional enrolment phase with repeated unconstrained initialisations is used to identify highly biased bits, then the cryptographic key generation becomes reliable, but the process time becomes excessively long
Solution Approach 1:
The patent applies preliminary action by performing biased initialisations that promote establishment in a first logic state before the actual key generation. This preliminary step pre-configures the memory cells to favor certain states, reducing the number of repeated initialisations needed during the enrolment phase to identify highly biased bits, thereby shortening the overall process time while maintaining reliability
Solution Approach 2:
The patent changes the initialisation parameters from unconstrained to biased initialisations. By controlling the initialisation process to promote establishment in a specific logic state, the statistical properties of the memory cells are modified, allowing faster identification of highly biased bits with fewer cycles, thus resolving the time-reliability contradiction
2Reliability
If non-volatile memory and error correction codes are used to store and recover enrolment results, then data security and reliability are improved, but the memory space requirement increases significantly
Solution Approach 1:
The patent extracts and eliminates the need for non-volatile memory and error correction codes by using volatile SRAM memory with biased initialisations. The biased initialisation process creates sufficiently stable patterns that can be directly used for key generation without requiring external storage or correction mechanisms, thereby removing the memory space burden while maintaining reliability
Solution Approach 2:
The patent replaces expensive, space-consuming non-volatile memory with volatile SRAM memory that is initialised repeatedly. The volatile nature of SRAM is compensated by the biased initialisation process, which ensures reliable key generation without requiring persistent storage, thus using simpler, smaller memory resources
3Reliability
If error correction code decoding is performed at each key generation request, then key generation reliability is maintained, but the processing time and computational complexity increase
Solution Approach 1:
The patent removes the error correction code decoding step from the key generation process by using biased initialisations that directly produce reliable results. The controlled initialisation process ensures that highly biased bits are consistently identified without requiring post-processing correction, thereby eliminating the time-consuming ECC decoding operation and improving key generation speed
Data Source
AI summary
A method is for generating a cryptographic key from an SRAM memory and device implements such a method. The method includes steps of biased initialisation of a first set of cells located in a first region of the SRAM memory so as to promote the establishment, in a first logic state, of the cells of the first set, storing, in a second set of cells of a second region of the memory, the respective states of the cells of the first set and resulting from the first biased initialisation, then, performing a second biased initialisation of the first set of cells so as to promote a setting in a second logic state, complementary to the first logic state, the cells of the first set. The method further includes, after the first biased initialisation and the second biased initialization, establishing an N-bit digital key.