Low-Power SRAM Cells Using Data-Dependent Bit Line Control
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Solution Overview
Problem
Existing SRAM cell designs face challenges in balancing reliability and low power consumption, particularly in deep sub-micron geometry silicon processing, where read and write operations require significant power and are vulnerable to noise due to unnecessary activation of access devices across multiple columns.
Innovation Solution
The design introduces a data-dependent conductive path between bit lines using MOS transistors, controlled by the state of the storage element, which eliminates the need for additional column select signals and reduces power consumption by only activating the necessary column during read and write operations, while maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional transistors are added to separate read and write paths (8-transistor design), then read stability is improved, but device complexity increases
Solution Approach 1:
The patent merges the read and write access paths by using the same access transistors for both operations. The bit lines themselves are used to control the activation of access transistors, eliminating the need for separate read and write word lines and reducing the transistor count while maintaining reliable operation.
Solution Approach 2:
The access transistors serve dual functions as both read and write access devices. The bit lines are used both for data transfer and for controlling the access transistor gates, making the same hardware components perform multiple functions and reducing overall device complexity.
2Ease of operation
If access devices are activated during read operations, then data can be read from the cell, but power consumption increases and noise vulnerability increases
Solution Approach 1:
The access transistors are activated only during the brief period when data needs to be read or written, controlled by the timing of bit line voltage transitions. During idle periods, the access transistors remain off, minimizing power consumption while maintaining read capability when needed.
Solution Approach 2:
The bit lines themselves serve dual purposes: they carry data and simultaneously control the gate voltages of the access transistors. This self-service mechanism eliminates the need for separate control signals, reducing power consumption and simplifying the control logic.
3Adaptability or versatility
If access devices are activated across multiple columns, then all cells can be accessed, but noise vulnerability increases and power consumption increases
Solution Approach 1:
The patent implements local control of access transistors through bit line voltage levels. Only the specific column or columns with high voltage on their bit lines will have their access transistors activated, while other columns remain isolated. This localized activation reduces noise coupling between columns and lowers overall power consumption.
Solution Approach 2:
The memory array is effectively segmented into independently controllable columns through the bit line controlled access mechanism. Each column can be selectively activated or deactivated based on its bit line voltage state, allowing precise control over which cells are accessible and reducing interference between adjacent columns.
Data Source
AI summary
The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having respective first and second storage access nodes (24, 26); first and second voltage lines (VSS, VDD 16a, 6b) across which said pair of back to back inverters (12a, 12b and 14a, 14b) are connected; a first access transistor (18a), connected to said first storage node (24); a second access transistor (18b), connected to said second storage node (26); a write word line (22) connected to a gate (18g1) on said first access transistor (18a) and a gate (18g2) on said second access transistor (18b); a first bit line (28) operably connected for controlling 10 said node (24); a second bit line (30) operably connected for controlling said node (26); in which there is provided a data dependent conductive path (46) between the first and second bit lines (28, 30).