Hierarchical Data Line Layout for SRAM Access Speed
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges with high line loading and slow data access times due to the large number of data lines and complex logical ORing operations, leading to increased delay times and data skew in static random access memory (SRAM) devices.
Innovation Solution
A hierarchical data line layout structure is implemented, with fewer upper data lines coupled to a data latch and dynamic CMOS logic type data line drivers performing logical ORing operations, reducing the number of data lines and optimizing the data path to enhance speed and reduce line loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of data lines are used to connect all memory cells to I/O terminals, then data access capability is improved, but line loading increases and access speed decreases
Solution Approach 1:
The patent divides the memory mat into multiple sub-mats, with each sub-mat having its own dedicated data lines and ORing unit. This segmentation reduces the number of data lines that need to be routed through the center of the memory mat, thereby reducing line loading and improving access speed while maintaining the ability to access all memory cells.
2Ease of operation
If data lines are routed through the center of the memory mat for logical ORing operation, then data transfer is achieved, but line loading increases and delay time increases
Solution Approach 1:
The patent segments the data lines into local data lines for each sub-mat and separate ORing units distributed throughout the memory mat. This eliminates the need for all data lines to converge at the center, reducing the routing distance and line loading, thereby decreasing delay time while maintaining data transfer functionality.
3Speed
If the number of sub-mats is increased to reduce memory cells per bit line, then read speed is improved, but the number of data lines increases causing more line loading
Solution Approach 1:
The patent segments the memory mat into multiple sub-mats, each with its own local data lines and ORing unit. This allows for increased numbers of sub-mats to improve read speed while the segmented architecture prevents corresponding increase in overall line loading, as each segment handles its own data independently.
Solution Approach 2:
The patent introduces a hierarchical structure with local data lines at the sub-mat level and global data lines at the memory mat level. This dimensional organization allows multiple sub-mats to operate in parallel without proportionally increasing the number of global data lines, thus improving read speed while controlling line loading.
4Ease of operation
If a conventional ORing unit with many inputs is used, then logical ORing operation is achieved, but operation speed decreases
Solution Approach 1:
The patent divides the conventional ORing unit into multiple smaller ORing units, each handling a subset of data lines. This segmentation reduces the number of inputs to each ORing unit, thereby improving operation speed while still achieving the logical ORing function across all data lines through the distributed architecture.
Data Source
AI summary
A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.