SRAM Data Retention Test Circuit Offset Voltage
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Solution Overview
Problem
Current methods for testing SRAM memory cells for weak or missing p-channel transistors are unreliable and time-consuming, as they cannot predictably detect faulty cells within a reasonable timeframe due to the indeterminate nature of data retention in such cells.
Innovation Solution
A method and circuitry are introduced to test SRAM cells by generating logic low and high signals with an offset, allowing the cell to achieve a memory state and determining if it retains the expected state, utilizing a data retention test circuit that reduces the logic high signal to a level corresponding to logic low plus an offset, enabling quicker and more reliable detection of p-channel transistor failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional data retention test is used to detect weak or missing p-channel transistors, then the test can identify faulty cells, but the test takes many seconds to complete and may still produce suspect results due to unpredictable retention times
Solution Approach 1:
The patent changes the voltage parameter by applying a reduced logic high signal (logic low plus an offset) instead of a full logic high signal. This voltage modification creates a stressed condition that accelerates the detection of weak p-channel transistors, allowing reliable detection within a single memory cycle rather than requiring extended waiting periods.
Solution Approach 2:
The patent applies the reduced logic high signal during the write operation itself, preparing the memory cell in a stressed state before the retention period begins. This preliminary action ensures that weak p-channel transistors are immediately exposed to conditions that will reveal their deficiency, eliminating the need for extended waiting periods.
2Reliability
If an extended waiting period is used in traditional testing to allow data retention to manifest, then more faulty cells can be detected, but the test becomes slower and less predictable
Solution Approach 1:
By modifying the voltage parameter to a reduced logic high level during the write operation, the patent creates a stressed condition that immediately exposes weak p-channel transistors. This eliminates the need for extended waiting periods while maintaining reliable fault detection, thereby increasing testing speed and productivity.
Solution Approach 2:
The patent rushes through the detection process by applying a stressed voltage condition during the write operation itself, allowing the test to complete in a single memory cycle. This skips the extended waiting period required by traditional methods, dramatically increasing testing speed while maintaining detection reliability.
3Reliability
If complement data is used to test both data states, then both logic 0 and logic 1 states can be verified, but the test complexity and time requirements increase
Solution Approach 1:
The patent applies the reduced logic high signal during the write operation itself, creating a stressed condition that immediately exposes weak p-channel transistors. This eliminates the need for extended waiting periods while maintaining reliable fault detection, thereby increasing testing speed and productivity.
Solution Approach 2:
The patent rushes through the detection process by applying a stressed voltage condition during the write operation itself, allowing the test to complete in a single memory cycle. This skips the extended waiting period required by traditional methods, dramatically increasing testing speed while maintaining detection reliability.
Data Source
AI summary
A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.