SRAM Deep Well Grids for Latchup Tolerance
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Solution Overview
Problem
Conventional CMOS integrated circuits are vulnerable to latchup and single-event upset (SEU) events, which can lead to soft and hard error failures, especially as feature sizes shrink, and the increased chip area required for well contacts to mitigate these issues becomes a significant cost in modern deep sub-micron manufacturing technologies.
Innovation Solution
A CMOS memory cell array is constructed using a single-well or double-well technology with deep well regions of opposite conductivity types underlying the memory cell array, forming a two-dimensional grid that connects surface wells of the same conductivity type, reducing parasitic resistance and increasing junction capacitance to enhance robustness against latchup and SEU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional well contact structures are used to mitigate latchup and SEU, then reliability is improved, but chip area increases
Solution Approach 1:
The patent introduces deep well regions that extend vertically into the substrate, transitioning from a two-dimensional surface well contact structure to a three-dimensional structure. This vertical extension increases the effective contact area and junction capacitance without proportionally increasing the horizontal chip area, thereby improving latchup tolerance while maintaining area efficiency
Solution Approach 2:
The deep well regions are nested within the substrate, with surface wells positioned above them. This nested configuration allows the deep wells to provide additional latchup protection and increased junction capacitance while sharing the same horizontal footprint as the surface wells, effectively multiplying the protective function within a compact space
2Productivity
If feature sizes are shrunk to increase memory capacity, then productivity is improved, but vulnerability to latchup and SEU increases
Solution Approach 1:
The patent changes the depth parameter of the well regions by introducing deep wells that extend significantly into the substrate. This parameter change increases the junction capacitance and reduces parasitic resistance, providing enhanced latchup protection and SEU tolerance that scales with the continued shrinkage of surface feature sizes for increased memory capacity
3Reliability
If deep well regions are added to reduce parasitic resistance, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple separate protective structures into a unified deep well system. By combining the latchup protection and SEU tolerance functions into the deep well regions that also serve as the foundation for surface wells, the design reduces the need for additional separate protective structures, thereby limiting the increase in device complexity while achieving improved reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces soft and hard error failure rates while allowing for the fabrication of integrated circuits in reduced chip area, maintaining electrical performance and improving latchup tolerance without the need for extensive well contact areas.
Implementation Method 1
reducing parasitic resistance
Implementation Method 2
increasing junction capacitance
Data Source
AI summary
An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.