SRAM De-initialization Circuit for Data Remanence Security
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Solution Overview
Problem
SRAM-based PUF circuits are vulnerable to attacks due to data remanence, where data persists after power down, making them susceptible to unauthorized access until charge dissipates.
Innovation Solution
Incorporating a de-initialization circuit that quickly erases SRAM values by equalizing signal states on complementary bit lines, either by short-circuiting or driving identical values, to create an unstable intermediate state based on manufacturing variations, thus protecting against unauthorized control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a de-initialization circuit is added to quickly erase SRAM values, then security against data remanence attacks is improved, but device complexity increases
Solution Approach 1:
The de-initialization circuit is merged with the existing SRAM bit line structure by utilizing the same bit lines for both normal operation and de-initialization. The circuit combines the de-initialization transistors with the existing access transistors and bit line infrastructure, allowing the SRAM to perform both data storage and secure erasure functions without adding completely separate circuit paths.
Solution Approach 2:
The bit lines serve dual purposes: during normal operation they carry read/write data signals, and during de-initialization they serve as discharge paths for the de-initialization transistors. This multi-functionality allows the same physical infrastructure to support both standard SRAM operations and security erasure functions without requiring dedicated separate circuits.
2Object-affected harmful factors
If de-initialization circuitry is incorporated into SRAM, then vulnerability to unauthorized access is reduced, but manufacturing complexity increases
Solution Approach 1:
The de-initialization transistors are selectively placed only at critical locations within the SRAM array where security erasure is most needed, rather than uniformly distributing complex de-initialization structures throughout the entire device. This localized approach minimizes the overall manufacturing complexity while providing adequate security coverage.
Solution Approach 2:
The de-initialization function is achieved by changing the operational state parameters of existing transistors through control signals rather than requiring fundamentally different transistor structures or materials. The same standard CMOS transistors used in normal SRAM operation are repurposed for de-initialization by adjusting their gate control signals, maintaining compatibility with standard fabrication processes.
3Loss of information
If the de-initialization circuit equalizes signal states on bit lines, then data remanence is eliminated, but signal state stability during operation may be affected
Solution Approach 1:
The de-initialization circuit equalizes the bit line states to a predetermined intermediate voltage level before the SRAM cells are fully powered down or before potential unauthorized access attempts. This preliminary equalization action ensures that even if power is interrupted or the device is attacked, the bit lines start from a known neutral state rather than retaining previous data values.
Solution Approach 2:
The bit line signal states are made dynamically controllable, transitioning between stable operational states during normal read/write operations and an equalized intermediate state during de-initialization. The circuit allows the bit lines to adapt their state based on operational mode, maintaining stability during normal use while enabling controlled equalization when security erasure is required.
Data Source
AI summary
Circuits and approaches for de-initializing memory circuits. In one implementation, a memory circuit includes a plurality of memory cells. Each memory cell includes a pair of cross-coupled inverters and first and second access transistors coupled to the pair of cross-coupled inverters. A first bit line is coupled to the first access transistor, and a second bit line is coupled to the second access transistor. A de-initialization circuit is coupled to the first and second bit lines. The de-initialization circuit is configured and arranged to equalize signal states on the first and second bit lines in response to a de-initialization signal.