SRAM DFT Shadow Latch Timing for Equal Output Hold
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Solution Overview
Problem
Existing SRAM circuits face challenges in maintaining output hold time consistency between normal operation and design-for-test (DFT) mode, leading to output hold degradation due to narrow time windows for valid data reading.
Innovation Solution
Implementing a timing path through the SRAM circuit that mirrors normal operation, using a timing delay circuit and multiplexer to ensure output hold time equality between DFT and normal modes by enabling a shadow latch and sense amplifier in DFT mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DFT mode is implemented in SRAM circuit, then testability is improved, but output hold time degrades due to narrow time windows
Solution Approach 1:
The patent segments the output path into two separate paths: a normal operation path and a DFT test path. The normal path maintains the original output hold characteristics, while the DFT path is specifically designed for test operations. This segmentation allows the DFT mode to be enabled without degrading the output hold time of the normal operation mode, as each path operates independently with its own timing characteristics.
Solution Approach 2:
The patent introduces an intermediary mechanism (multiplexer and control logic) that switches between the normal operation path and the DFT test path based on the operational mode. This intermediary allows the system to maintain the benefits of DFT (improved testability) while preserving the output hold characteristics of normal operation, as the intermediary manages the timing and switching between the two paths to prevent degradation.
2Reliability
If output hold time is maintained in DFT mode, then reliability is improved, but circuit complexity increases
Solution Approach 1:
The patent implements a universal output structure that serves both normal operation and DFT test functions. The same output buffer and timing circuitry are used in both modes, ensuring consistent output hold characteristics. The multiplexer acts as a universal switching element that routes signals appropriately based on mode, rather than creating entirely separate output paths. This multi-functionality approach maintains reliability while minimizing the increase in circuit complexity.
Solution Approach 2:
The patent merges the normal operation path and DFT test path at the output buffer stage, combining their functions into a unified output structure. This merging ensures that both paths benefit from the same output timing characteristics and drive capability, maintaining consistent output hold time. The control logic and multiplexer are integrated into the existing SRAM architecture, combining test functionality with normal operation without requiring completely separate circuits.
Data Source
AI summary
A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a memory circuit configured to receive a clock signal and generate an output signal. The memory circuit includes a timing delay circuit. The semiconductor device includes a design-for-test (DFT) circuit comprising a shadow latch. The DFT circuit is configured to receive an output of the timing delay circuit, and generate a DFT output signal via the shadow latch. A first output hold of the output signal is about equal to a second output hold of the DFT output signal.