SRAM Cell Design with Differential Beta Ratios for Write Margin
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Solution Overview
Problem
In deep sub-micron integrated circuit technology, existing SRAM cell designs using FinFETs face challenges such as current crowding, degraded write and read margins, and limitations in co-optimizing cell size, cell current, and Vcc, with additional fabrication costs due to the lack of freedom in tuning the alpha ratio for optimized read stability and write margin.
Innovation Solution
The design introduces two SRAM cells with different numbers of transistors, each with distinct threshold voltages and gate stacks, and a write-assist circuitry to dynamically adjust voltages, allowing for optimized alpha ratios and improved stability and margin performance, while simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the beta ratio is set close to 1 to reduce cell size, then the cell area is minimized, but current crowding occurs and write margin is degraded
Solution Approach 1:
The patent applies different beta ratios to different transistor types within the same SRAM cell. Specifically, pull-down devices use a first beta ratio while pass-gate devices use a second beta ratio, allowing local optimization of transistor dimensions to balance cell size reduction with adequate write margin and current distribution
Solution Approach 2:
The patent changes the beta ratio parameters differentially across transistor types. By setting the first beta ratio for pull-down devices and a second beta ratio for pass-gate devices, the invention optimizes the balance between cell area minimization and write operation reliability, preventing current crowding while maintaining compact cell dimensions
2Reliability
If the alpha ratio is increased to improve write margin, then write capability is enhanced, but read stability margin is degraded
Solution Approach 1:
The patent adjusts the alpha ratio parameter by differentiating the beta ratios between pull-down devices and pass-gate devices. This parameter optimization allows achieving adequate write margin while maintaining sufficient read stability margin, balancing the trade-off between write capability and read stability
Solution Approach 2:
The patent applies different beta ratio values to different transistor locations within the cell, which indirectly controls the alpha ratio. This local differentiation allows the circuit to achieve both good write margin and read stability without requiring extreme alpha ratio values
3Loss of energy
If FinFETs are used to reduce leakage in advanced technology nodes, then power consumption is reduced, but freedom to co-optimize cell size, cell current and Vcc is lost
Solution Approach 1:
The patent restores co-optimization freedom by introducing differential beta ratios that can be adjusted independently. This allows simultaneous optimization of cell size, cell current, and Vcc while maintaining the low leakage characteristics of FinFETs, as the beta ratio parameters provide additional degrees of freedom for circuit optimization
4Speed
If equal numbers of pull-down devices and pass-gate devices are used for high speed operation, then cell speed is improved, but cell size increases and alpha ratio tuning freedom is lost
Solution Approach 1:
The patent applies different beta ratios to pull-down devices and pass-gate devices, allowing unequal transistor dimensions to achieve the same effective drive strength. This enables high-speed operation with equal functional capability while minimizing cell size, as transistors can be sized differently based on their specific functional requirements rather than requiring equal numbers
Data Source
AI summary
The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size; and a second SRAM cell having a second cell size greater than the first cell size. The first SRAM cell includes first n-type field effect transistors (nFETs) each having a first gate stack. The second SRAM cell includes second nFETs each having a second gate stack different from the first gate stack.