On-Die SRAM Cache Direct Access Mode Switching

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Solution Overview

Problem

Current cache technologies, such as last level caches, primarily reduce memory access latency by storing data copies, but they do not allow direct access modes that could further enhance performance by enabling clients to explicitly access cache data without relying on backing memory, limiting potential latency reductions.

Innovation Solution

Implementing a technique that allows a portion of the last level cache to be used in a directly accessed manner, where clients can access data stored directly in the cache without a memory copy, and converting between cache and directly accessed modes based on client requests or system conditions, using memory mapping mechanisms to manage access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If cache data is accessed through backing memory, then data access is simplified and memory management is easier, but access latency increases and performance is limited

Engineering Contradiction:
Improvememory access latencyVSAvoidaccess mode management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements dynamic access mode switching for cache entries, allowing each entry to be accessed either through the cache directly or through backing memory based on real-time conditions. The cache controller dynamically determines the access path for each memory access request, enabling the system to adapt between low-latency cache access and simplified memory-accessed cache modes without requiring static configuration.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If the cache is used exclusively as a cache, then latency reduction is achieved, but direct access capability is lost and versatility is reduced

Engineering Contradiction:
Improveaccess mode flexibilityVSAvoidaccess latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent enables cache entries to serve multiple functions by supporting dual access modes. Each cache entry can function as a traditional cache entry accessed through the cache controller for latency-critical operations, or as a directly accessible memory-like storage for operations requiring explicit access. This multi-functionality allows the same cache hardware to adapt to different access patterns and performance requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12117935B2Technique to enable simultaneous use of on-die SRAM as cache and memory
Publication Date: 2024.10.15 ADVANCED MICRO DEVICES INC
  • US12117935B2 patent drawing
  • US12117935B2 patent drawing
  • US12117935B2 patent drawing

AI summary

A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.