Data Processing With SRAM-DRAM Threshold Storage
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Solution Overview
Problem
The increasing performance of processors, such as GPUs, makes it difficult to secure sufficient memory bandwidth for transferring intermediate computation results between the processor and external memory, leading to a potential need for high-speed memory or memory interface upgrades, which significantly increases system costs.
Innovation Solution
A data processing method that includes determining a threshold value for data transfer based on the cost of computation and data size, deciding whether to store computation results in a DRAM or an SRAM, thereby optimizing memory usage and reducing the need for high-capacity DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the processor performance is improved, then the computational capability is enhanced, but the memory bandwidth becomes insufficient for transferring intermediate computation results to external memory
Solution Approach 1:
The patent segments the memory hierarchy into multiple levels: high-speed SRAM caches within the processor core and external DRAM memory. By dividing memory storage into these segments with different performance characteristics, the system can utilize fast SRAM for frequently accessed intermediate results while using cost-effective DRAM for larger datasets, thereby maintaining high processor performance without requiring proportionally high memory bandwidth.
Solution Approach 2:
The patent introduces SRAM cache memory as an intermediary between the processor and external DRAM. This intermediary layer stores frequently accessed intermediate computation results close to the processor, reducing the need for continuous high-speed transfers to external memory. The SRAM acts as a buffer that mediates between computational needs and memory storage capabilities.
2Quantity of substance
If external memory is used to store intermediate computation results, then the memory capacity is increased, but the memory bandwidth becomes a bottleneck for data transfer
Solution Approach 1:
The memory system is segmented into capacity-providing DRAM and speed-providing SRAM components. DRAM handles large-capacity storage of complete datasets and less frequently accessed data, while SRAM handles high-speed storage of intermediate results. This segmentation allows the system to achieve both high memory capacity and adequate data transfer speed without requiring the entire memory system to operate at high bandwidth.
Solution Approach 2:
SRAM serves as an intermediary storage layer between the processor and external DRAM. It captures and stores intermediate computation results that require fast access, thereby reducing the bandwidth burden on the external memory interface. This intermediary approach allows external memory to provide large capacity without being constrained by bandwidth limitations for all data transfers.
3Speed
If high-speed memory or memory interface is developed to increase memory bandwidth, then the data transfer capability is improved, but the system cost greatly increases
Solution Approach 1:
The patent applies local quality by providing high-speed SRAM memory only where it is most needed - for storing intermediate computation results that require frequent access. The bulk of memory capacity is provided by more cost-effective DRAM. This localized application of high-performance memory reduces overall system cost compared to providing high-speed memory for all data storage needs.
Solution Approach 2:
The system uses inexpensive DRAM for the majority of memory storage needs, accepting that not all data requires high-speed access. Only the critical intermediate results are stored in expensive SRAM. This approach prioritizes cost-effectiveness for the bulk of data storage while providing high speed only where computationally necessary.
Data Source
AI summary
A data processing method includes a first processing which executes a first computation using first data to obtain second data, a second processing which executes a second computation using the second data, and storing, in a memory, the second data having a storing value greater than or equal to a predetermined storing value. The storing value is determined based on a cost of the first computation and a size of the second data.


