SRAM Driving Circuit Sequential Cell Access Power Optimization
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Solution Overview
Problem
SRAM memory devices face challenges in reducing power consumption and ensuring data stability during continuous writing and reading operations, particularly in mobile devices where power efficiency is crucial.
Innovation Solution
A memory device with a latch structure connected in a matrix form to word lines and bit line pairs, utilizing a driving circuit that sequentially programs or reads memory cells during an on period and precharges bit lines during an off period, reducing the number of word line on/off operations and optimizing bit line operations for power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If word line is switched on/off for each memory cell access, then data can be read/written sequentially, but power consumption increases due to frequent switching
Solution Approach 1:
The patent applies preliminary action by precharging bit lines before memory cell access and maintaining word line in on-state throughout the entire page read/write operation. The word line is pre-charged to on-state before accessing any memory cell in the page, and remains on during all subsequent accesses to n memory cells, eliminating repeated switching operations.
2Ease of operation
If bit line is precharged for each memory cell access, then data access is enabled, but power consumption increases due to repeated precharging operations
Solution Approach 1:
The patent merges multiple precharging operations into a single precharging event. Instead of precharging bit lines individually for each memory cell access, the system precharges all bit lines associated with the page once before the word line is activated, combining multiple operations into one to reduce power consumption.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining the word line in a continuous on-state throughout the entire page read/write operation. The word line remains activated from the first memory cell access through the last memory cell access without interruption, enabling continuous data access without repeated switching.
3Use of energy by moving object
If word line remains on during page read/write operation, then power consumption is reduced, but data stability may be compromised
Solution Approach 1:
The patent implements feedback mechanisms through sense amplifiers that continuously monitor bit line voltage levels during the read operation. The sense amplifiers detect changes in bit line voltage caused by leakage currents and compensate by adjusting readout timing and strength, ensuring data stability is maintained even with the word line in continuous on-state.
Data Source
AI summary
A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.