SRAM Cell Dual Pass Gate Transistors Read Write Stability
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Solution Overview
Problem
Conventional SRAM cells face challenges in achieving high Beta and Gamma ratios for stability during read and write operations, while being susceptible to manufacturing variations, leading to increased probabilities of soft errors.
Innovation Solution
The SRAM cell design features two pass gate transistors connected in parallel at each storage node, with independently controlled gate structures separated by a CT pillar, allowing for dual operating modes to optimize Beta and Gamma ratios during read and write operations, thereby enhancing stability and tolerance to manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM cell design with single pass gate transistor is used, then device complexity is low, but stability during read and write operations cannot be simultaneously optimized
Solution Approach 1:
The pass gate transistor is segmented into two separate transistors (first pass gate transistor and second pass gate transistor) with independent gate structures. This segmentation allows independent control of each transistor through separate word lines, enabling optimized Beta ratio during read operations and optimized Gamma ratio during write operations, thereby simultaneously achieving high stability for both operations while managing device complexity through systematic design
Solution Approach 2:
The patent implements dynamic operation modes where the dual pass gate transistors can be independently controlled. During read mode, one transistor is activated to optimize Beta ratio; during write mode, both transistors are activated to optimize Gamma ratio. This dynamic switching between operational states allows the system to adapt to different operational requirements, achieving high stability without permanently increasing device complexity
2Reliability
If high Beta ratio and high Gamma ratio are both optimized, then stability during read and write operations is improved, but manufacturing variations have greater impact on soft errors
Solution Approach 1:
The patent changes the operational parameters by introducing dual pass gate transistors with independent control, enabling the system to dynamically adjust Beta and Gamma ratios based on operational mode. This parameter flexibility compensates for manufacturing variations by allowing optimization during operation rather than requiring perfect manufacturing precision, thereby reducing the impact of soft errors from manufacturing variations
3Reliability
If dual pass gate transistors with independent gate structures are used, then Beta and Gamma ratios can be optimized for both operations, but layout area increases
Solution Approach 1:
The patent merges the source and drain regions of the two pass gate transistors into shared structures. The first and second pass gate transistors share common source and drain regions, which reduces the overall layout area compared to having completely separate transistors. This merging approach maintains the stability benefits of dual transistors while minimizing the increase in layout area
Data Source
AI summary
A static random access memory (SRAM) cell includes 1st and 2nd fins disposed on a substrate. A 1st pass gate transistor (1st PG) is embedded in the 1st fin. The 1st PG has a source region and a drain region disposed over the 1st and 2nd fins. A 1st gate structure (1st PG-G) is disposed over the 1st fin and between the source and drain regions. The 1st PG-G is electrically connected to a 1st word line. A 2nd pass gate transistor (2nd PG) is embedded in the 2nd fin. The 2nd PG has the same source and drain regions. A 2nd gate structure (2nd PG-G) is disposed over the 2nd fin and between the source and drain regions. The 2nd PG-G is electrically connected to a 2nd word line. A 1st CT pillar is disposed between the 1st PG-G and 2nd PG-G.