SRAM Write Timing via Dummy Bit Line Discharge
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Solution Overview
Problem
In integrated circuit memories, particularly SRAM, unintended partial read operations during write operations lead to increased write time and power consumption, especially in high-density architectures like FinFET processes, due to the assertion of word lines before bit line discharge, causing power wastage and reduced write robustness.
Innovation Solution
A row decoder with a word line delay logic circuit that delays the assertion of the addressed word line during a write operation until a dummy bit line is discharged, ensuring that the bit line is fully discharged before the word line is asserted, independent of the memory dimensions and process node, thus avoiding partial read operations and enhancing write speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the word line is asserted using the common timing path for read operations, then the word line is asserted early to enable fast access, but the bit line discharge is interrupted causing unintended partial read operations that lengthen write time
Solution Approach 1:
The patent introduces a preliminary action by discharging the dummy bit line before asserting the word line during write operations. This preliminary discharge of the dummy bit line (which models the actual bit line's discharge behavior) ensures that when the word line is subsequently asserted, the bit line is already in the appropriate state to receive the write signal without interruption from simultaneous read operations. This resolves the timing conflict by establishing the correct sequence: bit line discharge first, then word line assertion.
2Device complexity
If multiple columns are multiplexed to a given write driver, then the device complexity is reduced and density is improved, but unintended partial read operations occur in unselected columns wasting power
Solution Approach 1:
The patent introduces a dummy bit line as an intermediary element that models the electrical behavior of actual bit lines. This dummy bit line serves as a mediator between the write driver and the actual bit lines, allowing the system to test and control the discharge timing without affecting the actual memory operations. The dummy bit line's discharge is used to gate the word line assertion, preventing unintended partial read operations in unselected columns while maintaining the benefits of column multiplexing.
3Manufacturing precision
If negative bit line boost techniques are employed in high-density architectures, then manufacturing precision is improved, but unintended partial read operations are exacerbated increasing write time
Solution Approach 1:
The patent uses a dummy bit line as a copy or model of the actual bit line's electrical characteristics. This dummy bit line replicates the discharge behavior of real bit lines in high-density architectures, including the effects of negative bit line boost techniques. By testing and controlling the timing based on the dummy bit line's discharge rather than the actual bit lines, the system can achieve precise timing control that is independent of specific process nodes while avoiding the write time penalties associated with simultaneous read-write operations.
Data Source
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AI summary
A static random access memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.