SRAM Dummy Cell Sleep Scheme for Leakage Reduction
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in balancing power consumption, performance, and stability due to leakage currents and short circuit paths in SRAM bit cells, particularly when using multiple power supplies.
Innovation Solution
Implementing a memory system with dummy cells between regions, utilizing two ground connections - a zero volt ground reference and a floating node ground reference - to prevent short circuit paths and reduce leakage currents, allowing for efficient power management and performance optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple power supplies are used in SRAM bit cells, then performance and noise margins are improved, but leakage current increases due to short circuit paths and cross-coupled inverter current
Solution Approach 1:
The memory array is divided into multiple regions with independent ground connections. Each region can be independently powered down by raising its ground reference voltage, allowing selective power management without affecting the entire memory array. This segmentation enables individual region control while maintaining overall system stability.
Solution Approach 2:
A dummy cell is introduced as an intermediary between adjacent memory regions. This dummy cell acts as a buffer that prevents direct interaction between regions with different ground references, eliminating short circuit paths while allowing each region to maintain its own ground connection for independent power management.
2Quantity of substance
If transistor sizes are decreased to increase memory capacity, then storage density improves, but threshold voltage variation increases causing performance degradation and state loss
Solution Approach 1:
Each memory region is provided with its own independent ground connection and power management control, allowing local optimization of operating conditions. This enables tailored voltage references for specific regions based on their threshold voltage characteristics and operational requirements, compensating for variations caused by smaller transistor sizes.
3Loss of energy
If sleep mode is implemented to reduce power consumption, then leakage current decreases, but short circuit paths can still occur between regions with different ground references
Solution Approach 1:
The dummy cell serves as an intermediary barrier between adjacent memory regions operating in different power states. When one region is in sleep mode with a raised ground reference and another is active with a zero volt ground, the dummy cell prevents direct current paths between these regions, eliminating short circuit hazards while preserving the power-saving benefits of sleep mode.
Solution Approach 2:
The potential harmful effect of having multiple ground references is converted into a beneficial feature. By allowing different regions to have different ground references, the system enables independent power management and sleep mode operation, with the dummy cell managing the interface between regions to prevent harmful short circuits.
Data Source
AI summary
A system and method for providing efficient power, performance and stability tradeoffs of memory accesses are described. A computing system uses a memory for storing data, and a processing unit, which generates access request. The memory stores data and includes a dummy cell between a first region and a second region. The first region and the second region operate with at least one of two operating states such as an awake state and a sleep state. The dummy cell uses two ground connections to support two separate ground references. In one example, a first ground reference is zero volts and a second ground reference is a floating node. In another example, the first ground reference is a value shared by one of the two regions and the second ground reference is the floating node.