SRAM Write Assist Using Dummy Cell Switches
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Solution Overview
Problem
Static random access memory (SRAM) devices face challenges in enhancing write performance without increasing occupied area, as existing write assist operations may not effectively reduce the resistance of bit and complementary bit lines during write operations.
Innovation Solution
The introduction of auxiliary bit and complementary bit lines, along with a switch circuit using transistors from dummy cells, which electrically connect bit and complementary bit lines to auxiliary lines based on the logic level of data to be written, reducing the effective resistance and enhancing write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write assist operation is performed using conventional methods, then write performance is improved, but occupied area increases
Solution Approach 1:
The dummy cells, which would otherwise be non-functional or wasted resources, are utilized to provide write assist functionality. The transistors from dummy cells are repurposed as switch circuits to reduce resistance during write operations, allowing the memory device to serve itself and eliminate the need for additional dedicated write assist structures.
Solution Approach 2:
The invention changes the functional state of dummy cells from inactive to active during write operations. By dynamically controlling the resistance of bit lines through the switch circuit formed by dummy cell transistors, the system adapts parameters (resistance) to improve write performance without permanent structural changes or additional area.
2Speed
If resistance of bit lines is reduced to improve write performance, then write speed is improved, but device complexity increases
Solution Approach 1:
The switch circuit formed by dummy cell transistors serves multiple functions: it acts as a resistance control element during write operations, utilizes existing dummy cell structures, and integrates with the conventional memory cell array without requiring separate dedicated write assist circuitry. This multi-functionality reduces overall device complexity while improving write speed.
Data Source
AI summary
A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.