SRAM Bit Cells With Dummy Structures For Fin Uniformity
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Solution Overview
Problem
Asymmetries in variable pitch layouts during double patterning in semiconductor fin fabrication for SRAM bit cells lead to variations in critical dimensions, affecting the performance and reliability of static random access memory (SRAM) devices.
Innovation Solution
The introduction of a deep trench isolation region and the use of mandrels with different etch selectivities, along with spacer layers, to reduce asymmetry and variations in fin dimensions, and the formation of semiconductor fins with specific arrangements to minimize etch loading and enhance uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable pitch layout is used for semiconductor fins in SRAM bit cells, then the layout flexibility and device functionality are improved, but asymmetries in the layout cause variations in critical dimensions due to etch loading during double patterning
Solution Approach 1:
The patent applies asymmetry by introducing a dummy fin structure that is intentionally asymmetric in position relative to the bit cell center. This dummy fin is placed closer to one set of actual fins than the other, creating an asymmetric compensation mechanism that balances the etch loading across different fin regions, thereby reducing critical dimension variations while maintaining the asymmetric variable pitch layout
Solution Approach 2:
The patent applies local quality by adding a dummy fin structure specifically in regions where etch loading causes critical dimension variations. The dummy fin is positioned locally to compensate for etch loading asymmetries in specific areas of the bit cell, allowing different regions to have optimized fin characteristics tailored to their local etch loading conditions
2Productivity
If multiple patterning technique is used to pattern semiconductor fins, then the fin density and device functionality are improved, but asymmetries in the layout result in variations in critical dimensions due to etch loading
Solution Approach 1:
The patent applies asymmetry by positioning the dummy fin structure asymmetrically with respect to the bit cell center and the actual fin structures. This asymmetric placement is specifically designed to counterbalance the asymmetric etch loading effects that occur during multiple patterning, thereby achieving uniform critical dimensions across all fins despite the asymmetric layout and multiple patterning process
Solution Approach 2:
The dummy fin structure acts as an intermediary element that mediates the etch loading effects between different fin regions. By introducing this intermediate dummy fin structure, the patent balances the etch loading across the bit cell, ensuring that the actual fins receive uniform etch treatment and maintain consistent critical dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved uniformity and reduced variations in critical dimensions of semiconductor fins, enhancing the performance and reliability of SRAM bit cells by minimizing etch loading and maintaining consistent fin dimensions across the bit cells.
Implementation Method 1
Asymmetries present in the variable pitch layout can result in variations in the critical dimensions of the semiconductor fins within a single SRAM bit cell due to etch loading during double patterning
Data Source
AI summary
Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.