SRAM Read-Modify-Write Circuit With Dynamic Self-Time Delay
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Solution Overview
Problem
Existing SRAM circuits for read-modify-write operations in a single clock cycle suffer from high power consumption due to multi-cycle operations and external data calculation, leading to significant bit line discharge and increased power expenditure.
Innovation Solution
Implementing a data modification circuit within the SRAM that performs the mathematical modify operation internally, combined with a dynamically variable self-time delay controlled by the read count value, allowing the entire operation to be completed in a single clock cycle with reduced bit line discharge and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the mathematical modify operation is performed externally to the SRAM, then the SRAM structure remains simple, but power consumption increases due to multi-cycle operations and data signal toggling
Solution Approach 1:
The data modification circuit is merged with the SRAM internal structure, combining the memory array, data sensing circuit, data modification circuit, and data writing circuit into a single integrated unit. This merging eliminates the need for external data modification operations and reduces multi-cycle operations to a single clock cycle, thereby reducing power consumption while maintaining a unified compact structure.
2Reliability
If the self-time delay duration is extended to ensure complete mathematical modification, then operation reliability is improved, but bit line discharge increases and power consumption rises
Solution Approach 1:
The self-time delay duration is made dynamically variable based on the read count value. The delay circuit adjusts the delay duration according to the magnitude of the count value, providing just enough time for the mathematical modification operation to complete. This dynamic adjustment ensures operational reliability while minimizing unnecessary delay and reducing bit line discharge and power consumption.
3Productivity
If the read-modify-write operation is completed in a single clock cycle, then productivity is improved, but the circuit complexity increases due to internal data modification circuit integration
Solution Approach 1:
The SRAM is segmented into distinct functional circuits: memory array, data sensing circuit, data modification circuit, and data writing circuit. Each segment performs a specific function within the single clock cycle, allowing parallel operation and completing the read-modify-write operation in one cycle. This segmentation manages complexity by organizing functions into modular units while achieving high productivity.
4Use of energy by moving object
If the data modification circuit is integrated within the SRAM, then power consumption is reduced by eliminating data toggling, but the area occupied by the SRAM increases
Solution Approach 1:
The integrated SRAM structure performs multiple functions within a single device: data reading, mathematical modification, and data writing. The data modification circuit is designed to work specifically with the SRAM's data structure, performing increment or decrement operations directly on the stored values. This multi-functionality reduces the need for separate external circuits and minimizes overall system area while reducing power consumption through eliminated data toggling.
Data Source
AI summary
A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location in response to assertion of control signal having a dynamically variable delay dependent on the current data word. The operations are advantageously performed within a single clock cycle.